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Data Transfer Between Subarrays in Memory

A sub-array and memory technology, applied in the field of semiconductor memory, can solve problems affecting data processing time and so on

Active Publication Date: 2021-06-29
MICRON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the possibility to perform other functions besides processing operations, such as read and write operations, can affect the data processing time of the processing means in the memory

Method used

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  • Data Transfer Between Subarrays in Memory
  • Data Transfer Between Subarrays in Memory
  • Data Transfer Between Subarrays in Memory

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0017] The present invention includes apparatus and methods for data transfer between sub-arrays in a memory. As described herein, an example apparatus may include a first subarray of memory cells and a second subarray of memory cells, wherein a first portion of memory cells of the first subarray and a first portion of memory cells of the second subarray are coupled to A first sensing circuit strip. The example apparatus can also include a third subarray of memory cells, wherein a first portion of the memory cells of the third subarray are coupled to a second sense circuit stripe, and wherein a second portion of the second subarray The memory cells and the memory cells of the second portion of the third sub-array are coupled to a third sense circuit stripe. A particular row of the second array may contain cells from the second array coupled to memory cells from the second array by coupling the memory cells from the first portion to adjacent memory cells from the second portio...

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Abstract

The present invention includes apparatus and methods for data transfer between sub-arrays in a memory. Examples may include a first sub-array of memory cells and a second sub-array of memory cells, wherein a first portion of memory cells of the first sub-array and a first portion of memory cells of the second sub-array are coupled to a first sensing circuit Bands. The third sub-array of memory cells can include memory cells coupled to the first portion of the second sense circuit stripe. A second portion of memory cells of the second sub-array and a second portion of memory cells of the third sub-array can be coupled to a third sense circuit strip. A particular row of the second array may include memory cells from the first portion of memory cells in the second array coupled to memory cells from the second portion of memory cells in the second array.

Description

technical field [0001] The present disclosure relates generally to semiconductor memory and methods, and more particularly, to apparatus and methods for data transfer between sub-arrays in memory. Background technique [0002] Memory devices are often provided as internal semiconductor integrated circuits in computers or other electronic systems. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data (eg, host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous Dynamic Random Access Memory (SDRAM) and Thyristor Random Access Memory (TRAM), etc. Non-volatile memory can provide permanent data by retaining stored data when power is not supplied and can include NAND flash memory, NOR flash memory, and resistive variable memory such as phase change random access memory (PCRAM), resistive random ac...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/06G11C16/26
CPCG11C16/06G11C16/26G11C5/025G11C7/06G11C7/1006G11C11/4091G06F3/0647
Inventor J·T·扎沃德恩G·E·胡申R·C·墨菲
Owner MICRON TECH INC