A method for developing and debugging a multi-core DSP program, a program document and a loading method

A technology of program development and debugging method, which is applied in the direction of multi-program device, program control design, software testing/debugging, etc., can solve problems such as program development and maintenance difficulties, achieve the effect of reducing the number of program documents and improving development efficiency

Inactive Publication Date: 2018-12-18
CHINESE AERONAUTICAL RADIO ELECTRONICS RES INST
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Problems solved by technology

If you use 4 pieces of 8-core DSP and adopt the traditional development method, you need to create at least 32 DSP program files, which is very difficult for program development and maintenance

Method used

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  • A method for developing and debugging a multi-core DSP program, a program document and a loading method
  • A method for developing and debugging a multi-core DSP program, a program document and a loading method
  • A method for developing and debugging a multi-core DSP program, a program document and a loading method

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Embodiment Construction

[0034] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

[0035] The multi-core DSP underlying driver will provide variables for identifying each DSP core, support multiple DSP cores to be developed with a set of program codes, and divide the functions completed independently and jointly by each DSP core through the core serial number. It provides the basis for program development and debugging. However, each core of DSP executes functions in parallel. For the code segment executed by multiple cores, the definition and use of variables and functions are exactly the same. Therefore, after the program is loaded and run, multiple DSP cores will access the same memory at the same time. space, resulting in program execution errors. Therefore, the traditional multi-core DSP development method avoids the situation that multiple cores occupy the same memory at the same time by creating a separate program fi...

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Abstract

A method for developing and debugging a multi-core DSP program includes such steps as carrying out chip numbering on each DSP chip by an FPGA chip to obtain core number of each DSP core inside the DSPchip; 2, dividing the physical address of the DSP core in the DDR according to the logical address of the private space of the DSP core in the DDR, changing the logical address of the private space of each DSP core in the DDR of the same DSP chip to the logical address of the same DDR, and establishing a mapping relationship between the logical address and the physical address; 3, compiling a multi-core DSP program document. In the multi-core DSP program document, the core function of each DSP core and the logical address of the core function in DDR private space are determined by chip numbers and core numbers, and. The invention fuses the codes of a plurality of DSP cores into a source code document, and the functions of each DSP core are distinguished by a core number and a chip number,thereby improving the development and debugging efficiency.

Description

technical field [0001] The invention relates to a method for realizing efficient development and debugging of a multi-core digital signal processor (Digital Signal Processor, hereinafter referred to as DSP) program. Background technique [0002] In the integrated avionics system, radio frequency systems such as radar, electronic warfare, communication, navigation, and identification gradually adopt generalized and integrated processors to complete signal and data processing. The processor includes processing devices such as Field Programmable Gate Array (Field Programmable Gate Array, hereinafter referred to as FPGA), DSP, and Central Processing Unit (Central Processing Unit, hereinafter referred to as CPU), which respectively complete the timing control, algorithm implementation and state management of the system. Usually undertake the main calculation work of the entire signal processor, and complete the realization of the core processing algorithm of the radio frequency s...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/36G06F9/50
CPCG06F9/5027G06F11/362
Inventor 吴敏宋琦弘李裕羿昌宇张海辉段瀚林朱海锋张亦居
Owner CHINESE AERONAUTICAL RADIO ELECTRONICS RES INST
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