A vsc-hvdc linear active disturbance rejection control method for improving system transient stability
A technology of VSC-HVDC and linear active disturbance rejection, which is applied in the field of VSC-HVDC linear active disturbance rejection control to improve the transient stability of the system. The effect of transient stability and strong robustness
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[0017] This embodiment provides a VSC-HVDC linear active disturbance rejection control method for improving system transient stability. Based on LADRC, a VSC-HVDC linear active disturbance rejection controller for improving system transient stability is designed to drive different operating modes. The power system under the condition stabilizes at a new equilibrium point as soon as possible after a fault. The flowchart of the method is as figure 1 shown, including the following steps:
[0018] Step 1. According to the controllability of VSC-HVDC to synchronous generator sets, divide the controllable units corresponding to VSC-HVDC, and aggregate each controllable unit into an equivalent controllable unit; combine VSC-HVDC and its corresponding The equivalent controllable unit is established as an equivalent controllable system; the controllability is determined by the acceleration factor c, and the controllable unit is a collection of synchronous generating units with obvious...
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