Dual bridge architecture of domestic feiteng processor

A processor and dual-bridge technology, applied in electrical digital data processing, instruments, etc., can solve the problem of not taking into account the low-speed external IO interface and high-speed PCI-E resource expansion, etc., to achieve strong versatility and practicability, improve Flexibility, the effect of improving overall performance

Active Publication Date: 2019-01-15
BEIJING INST OF COMP TECH & APPL
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AI Technical Summary

Problems solved by technology

[0006] The purpose of the present invention is to provide a dual-bridge equalization scheme for a domestic Phytium processor to solve the problem that the traditional single-bridge design cannot take into account both low-speed external IO interfaces and high-speed PCI-E resource expansion

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  • Dual bridge architecture of domestic feiteng processor

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Embodiment Construction

[0014] In order to make the purpose, content, and advantages of the present invention clearer, the specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

[0015] figure 1 Shown is a schematic diagram of the dual-bridge chip architecture of the domestic Phytium processor, such as figure 1 As shown, the dual-bridge architecture of domestic Phytium processor includes: domestic Phytium processor A1, low-speed bridge B1, high-speed bridge B2, SATA interface D1, network interface D2, USB interface D3 and PCI-E expansion slot D4- D6.

[0016] Such as figure 1 As shown, the domestic Phytium processor is different from the existing X86 architecture processor. Its own expansion resources are less, and there is no supporting north-south bridge solution. The USB, storage and other peripheral expansion resource controllers commonly used in computers have not been integrated. The d...

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Abstract

The invention discloses a dual-bridge chip structure of a domestic feiteng processor, wherein, the dual-bridge chip structure of the domestic feiteng processor comprises a feiteng processor, a low-speed bridge chip, a high-speed bridge chip, a SATA interface, a network interface, a USB interface and a plurality of PCI-E expansion grooves; the Feiteng processor and the PCI-E expansion groove are connected with the expansion slot, and the low-speed bridge piece and the flying processor are connected with each other through the PCI-E2.0 signal bi-directional connection, high-speed bridge and flying processor via PCI-E3.0 signal bi-directional connection. The low-speed bridge chip is connected with SATA controller, network controller and USB controller through PCI-E2.0 signal bi-directional connection; the SATA interface and the SATA controller are bidirectionally connected through the SATA signal. The network interface is bidirectionally connected with the network controller through the network signal. USB interface and USB controller are bidirectionally connected through USB signal; High Speed Bridge are connected with Multiple Other PCI-E Expansion slots via PCI-E3.0 signal bi-directional connection.

Description

technical field [0001] The invention relates to a bridge scheme, in particular to a dual-bridge equalization architecture of a domestic Phytium processor. Background technique [0002] With the continuous development of self-controllable information technology and the continuous improvement of domestic processor performance, the function and performance requirements of self-controllable servers based on domestic processors are getting higher and higher. At present, the commonly used domestic processors mainly include Phytium, Loongson, Shenwei and other platforms. Phytium processors are widely used in the field of domestic servers due to their excellent performance, good ecology and perfect function adaptation. [0003] Domestic Phytium processors are different from traditional X86 architecture processors in that they have less expansion resources. Commonly used peripheral expansion resource controllers such as USB and storage have not been integrated. PCIE3.0 interface, al...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/42
CPCG06F13/4282G06F2213/0026
Inventor 张鲁峰胡晗周魏
Owner BEIJING INST OF COMP TECH & APPL
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