Unlock instant, AI-driven research and patent intelligence for your innovation.

Channel error identification with pseudo-random binary sequence

A pseudo-random binary and channel technology, applied to instruments, circuits, electrical solid-state devices, etc., can solve the problems of expensive and inefficient memory and logic testing

Active Publication Date: 2019-02-26
CREDO TECH GRP LTD
View PDF15 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, memory and logic testing of 2.5D ICs can be expensive and inefficient, involving large areas on the IC die and external devices for generating test signals
Also, such testing may only target general problem areas rather than specific error locations

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Channel error identification with pseudo-random binary sequence
  • Channel error identification with pseudo-random binary sequence
  • Channel error identification with pseudo-random binary sequence

Examples

Experimental program
Comparison scheme
Effect test

example 1

[0026] Example 1: A device comprising a first die including a PRBS generator outputting test signals on parallel channels. The device further includes a second die including a PRBS checker that compares at least a portion of the test signal to a reference signal to identify a particular lane associated with an error .

example 2

[0027] Example 2: A method comprising generating a test signal comprising at least a portion of a PRBS. The method further includes transmitting the test signal on parallel channels. The method further includes comparing at least a portion of the test signal to a reference signal. The method further includes identifying a particular channel associated with an error based on the comparison.

example 3

[0028] Example 3: A 2.5-dimensional integrated circuit comprising a first die including a PRBS generator outputting test signals on parallel channels. The integrated circuit further includes a second die including a PRBS checker that compares at least a portion of the test signal to a reference signal to identify a specific error associated with the error. aisle. The integrated circuit further includes an interposer coupled to a printed circuit board, the interposer coupled to the first and second dies, the interposer including the parallel channels.

[0029] The following features may be incorporated into the various embodiments described above, either alone or in combination with one or more of the other features. The test signal may include n-bit PRBS, one bit per channel, generated by the PRBS generator and output in parallel, where n is a power of two. The second die may include an decimator that outputs an n-bit word to the PRBS checker by selecting each nth bit of the...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The application discloses a device and method for identifying a channel error by using a pseudo-random binary sequence. A device comprises a first tube core including a pseudo-random binary sequence (PRBS) generation device for outputting a testing signal at a parallel channel. Besides, the device also includes a second tube core including a PRBS checker for comparing at least one part of the testing signal with a reference signal to identify a specific channel associated with an error.

Description

Background technique [0001] Integrated circuits ("ICs") are incorporated into many electronic devices. IC packaging has evolved so that multiple ICs can be joined together vertically in so-called three-dimensional ("3D") packages in order to save horizontal area on a printed circuit board ("PCB"). Another packaging method, referred to as 2.5D IC packaging, incorporates an interposer, which may be formed from a semiconductor material such as silicon, to couple one or more dies to a PCB. However, memory and logic testing of 2.5D ICs can be expensive and inefficient, involving large areas on the IC chip and external devices for generating test signals. Additionally, such testing may only locate general problem areas rather than specific error locations. Contents of the invention [0002] Accordingly, in order to identify specific channel errors, systems, methods, and devices are disclosed herein that use a pseudo-random binary sequence ("PRBS"). An illustrative device includ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28
CPCG01R31/2896H01L24/16H01L25/0655H01L2224/16227H01L2924/15192H01L2924/1531G01R31/31717H01L23/5383G01R31/31703H01L23/5386H01L25/18G01R31/3177
Inventor 李中楠戴逸飞
Owner CREDO TECH GRP LTD
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2025 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com