A Dynamically Reconfigurable Convolutional Neural Network Accelerator Architecture for the Internet of Things

Abstract

The present invention is a dynamic reconfigurable convolutional neural network accelerator architecture for the Internet of Things field, including a cache architecture, etc. The cache architecture is used to store data from external storage or data generated during the calculation process, and organize and arrange them , is transmitted to the processing unit array in a data structure for calculation; the processing unit array is used to receive data from the cache architecture, and is stored in the cache architecture after convolution operation processing; the calculation module is used to receive data from the processing unit array, select Perform three operations of pooling, normalization, or activation functions, and store the output data in the cache architecture; the controller is used to send commands to the cache architecture, processing unit array, and computing module, and is designed with an external interface for communicating with the outside system to communicate. The present invention improves the performance of the convolutional neural network accelerator and reduces power consumption by designing a processing unit array with high parallelism and high utilization rate and a cache architecture that can increase the data multiplexing rate.

Description

technical field [0001] The invention belongs to the field of neural network accelerators, and in particular relates to a dynamic reconfigurable convolutional neural network accelerator architecture for the Internet of Things field. Background technique [0002] Artificial intelligence is one of the current popular computer sciences. As the main way to realize artificial intelligence, deep learning has also achieved profound development. As the number of network layers and the number of neurons in each layer increase, the computational complexity of the model will increase with As the size of the network increases, it grows exponentially. Therefore, the bottleneck of learning speed and running speed of deep learning algorithms is increasingly dependent on large-scale computing platforms such as cloud computing. For the hardware acceleration of deep learning algorithms, there are currently three types of implementations—multi-core CPUs, GPUs, and FPGAs. Their common feature i...

AI Technical Summary

Problems solved by technology

However, the existing hardware implementation has high power consumption and low energy efficiency (performance / power consumption), and cannot be applied to smart mobile terminals, such as smartphones, wearable devices or self-driving cars. Wait

In this context, reconfigurable processors have been proven to be a form of parallel computing architecture with both high flexibility and high energy efficiency. Improving processing performance while using a dedicated processor is one of the solutions to the limitations of the further development of multi-core CPU and FPGA technology, and may become one of the solutions for realizing high-performance deep learning SoC in the future

Images