D-latch resistant to double-node flipping

Abstract

The anti-double-node flipping D latch belongs to the field of anti-nuclear hardening in the reliability of integrated circuits. The present invention solves the problems that the existing latch requires more hardware, large area, high power consumption, long propagation delay time, poor ability to resist double-node flipping, and failure to realize fault tolerance to double-node flipping. The present invention includes 20 NMOS transistors N1 to N20, and 12 PMOS transistors P1 to P12, and uses few devices, small size and simple structure. Because of the few devices used, the power consumption of the entire latch is reduced and the hardware overhead is low . The signal at the input terminal of the latch can be transmitted to the output port through only one transmission gate, the data transmission time is short, and it can also realize the fault tolerance to any single-node and double-node flipping, so as to realize the fault-tolerant protection against single-node and double-node flipping. The invention is particularly suitable for applications with nuclear radiation effects in aerospace, spaceflight, nuclear power plants and the like.

Description

technical field [0001] The invention belongs to the field of anti-nuclear hardening in integrated circuit reliability. Background technique [0002] D latches are widely used in various digital integrated circuits, such as decoders and timing control circuits. However, since the latch has the function of storing information, radiation particles will change the information it holds, thus causing errors in the electronic system. [0003] Existing latches generally use three-mode redundancy or even more mode redundancy to achieve resistance to interference from external radiation particles. However, it requires a lot of hardware (up to 102 transistors), large area, and high power consumption. , Propagation delay time is long, and although anti-double-node flipping can be realized, the ability to resist double-node flipping is poor, and even the fault tolerance to double-node flipping cannot be realized. Therefore, the above problems need to be solved urgently. Contents of th...

AI Technical Summary

Problems solved by technology

[0004] The present invention aims to solve the problems that existing latches require more hardware, large area, high power consumption, long propagation delay time, poor ability to resist double-node flipping, and failure to realize fault tolerance to double-node flipping. Provides a new type of double-node flip-resistant D-latch

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