Low-redundancy anti-double-node-upset D latch

Abstract

The invention discloses a low-redundancy anti-double-node-upset D latch and belongs to the field of nuclear hardening in integrated circuit reliability. The problems that according to a conventional anti-radiation D latch, required hardware is much; power consumption is high; delay time is long; and double-node-upset resistance can be realized, but anti-double-node-upset capability is poor, or even, fault tolerance to double-node-upset cannot be realized are solved. The D latch comprises NMOS transistors N1 to N20 and PMOS transistors P1-P20. Employed devices are few. A size is small. A structure is simple. The employed devices are few, so power consumption of the whole latch is reduced, and hardware cost is relatively low. A signal at an input end of the latch can be transmitted to an output port through a transmission gate. Data transmission time is short. The fault tolerance to any single-node and double-node-upset can be realized, so anti-single-node and anti-double-node-upset fault tolerance protection is realized. According to the D latch, protection for application of an integrated circuit chip to a high radiation environment (such as aerospace and a ground nuclear power plant) can be provided.

Description

technical field [0001] The invention belongs to the field of anti-radiation reinforcement in integrated circuit reliability. Background technique [0002] In aerospace and high-radiation applications on the ground, the D latch needs to be hardened against radiation, mainly to prevent the stored data from being changed by external radiation particles. The traditional anti-radiation D latch is generally reinforced by triple-mode redundancy. The disadvantages are that it requires more hardware (up to 102 transistors), high power consumption, long delay time, and although it can achieve anti-double node flipping, However, the ability to resist double-node flipping is poor, and it is even impossible to achieve fault tolerance to double-node flipping. Therefore, the above problems need to be solved urgently. Contents of the invention [0003] The present invention aims to solve the problem that the traditional anti-radiation D latch needs more hardware, high power consumption,...

AI Technical Summary

Problems solved by technology

[0003] The present invention aims to solve the problem that the traditional anti-radiation D latch needs more hardware, high power consumption, long delay time, and although it can realize anti-double-node flipping, it has poor anti-dual-node flipping ability, and even cannot realize double-node flipping. For the fault-tolerant problem of node flipping, the present invention provides a low-redundancy anti-double-node flipping D latch

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