Low-redundancy anti-double-node-upset D latch

A dual-node flip and latch technology, applied in the direction of pulse generation, electrical components, and electric pulse generation, can solve problems such as high power consumption, long delay time, and multiple hardware

Inactive Publication Date: 2019-03-29
ZHONGBEI UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] The present invention aims to solve the problem that the traditional anti-radiation D latch needs more hardware, high power consumption, long delay time, and although it can realize anti-double-node flipping, ...

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Embodiment Construction

[0070]The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0071] It should be noted that, in the case of no conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other.

[0072] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

[0073] see figure 1 Describe this implementation mode, the low-redundancy anti-double-node flip D latch des...

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Abstract

The invention discloses a low-redundancy anti-double-node-upset D latch and belongs to the field of nuclear hardening in integrated circuit reliability. The problems that according to a conventional anti-radiation D latch, required hardware is much; power consumption is high; delay time is long; and double-node-upset resistance can be realized, but anti-double-node-upset capability is poor, or even, fault tolerance to double-node-upset cannot be realized are solved. The D latch comprises NMOS transistors N1 to N20 and PMOS transistors P1-P20. Employed devices are few. A size is small. A structure is simple. The employed devices are few, so power consumption of the whole latch is reduced, and hardware cost is relatively low. A signal at an input end of the latch can be transmitted to an output port through a transmission gate. Data transmission time is short. The fault tolerance to any single-node and double-node-upset can be realized, so anti-single-node and anti-double-node-upset fault tolerance protection is realized. According to the D latch, protection for application of an integrated circuit chip to a high radiation environment (such as aerospace and a ground nuclear power plant) can be provided.

Description

technical field [0001] The invention belongs to the field of anti-radiation reinforcement in integrated circuit reliability. Background technique [0002] In aerospace and high-radiation applications on the ground, the D latch needs to be hardened against radiation, mainly to prevent the stored data from being changed by external radiation particles. The traditional anti-radiation D latch is generally reinforced by triple-mode redundancy. The disadvantages are that it requires more hardware (up to 102 transistors), high power consumption, long delay time, and although it can achieve anti-double node flipping, However, the ability to resist double-node flipping is poor, and it is even impossible to achieve fault tolerance to double-node flipping. Therefore, the above problems need to be solved urgently. Contents of the invention [0003] The present invention aims to solve the problem that the traditional anti-radiation D latch needs more hardware, high power consumption,...

Claims

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Application Information

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IPC IPC(8): H03K3/3562
CPCH03K3/3562
Inventor 郭靖
Owner ZHONGBEI UNIV
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