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method and a device for eliminating a signal edge slope value influenced by Ledge

A signal and slope technology, used in special data processing applications, complex mathematical operations, instruments, etc., can solve problems affecting edge slope values, etc.

Active Publication Date: 2019-04-05
ZHENGZHOU YUNHAI INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The present invention proposes a method for eliminating the edge slope value of the signal affected by Ledge in order to solve the problem of the edge slope value of the clock signal test affected by the Ledge in the prior art. By adopting this method, the existing measurement waveform scheme can be used, The waveform is collected outside the chip package, and the measured waveform is calculated for the first-order derivative and the average value of the first-order derivative is obtained. After the slope waveform is obtained, it is added to calculate the signal equivalent to the die terminal of the chip package. The edge slope value eliminates the influence of the Ledge generated by the edge of the measurement signal waveform caused by signal reflection on the accuracy of the measurement data, improves the accuracy of the clock signal test data, and accurately judges and evaluates the signal quality of the R&D design

Method used

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  • method and a device for eliminating a signal edge slope value influenced by Ledge
  • method and a device for eliminating a signal edge slope value influenced by Ledge

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Effect test

Embodiment 1

[0036] Such as image 3 As shown, a method for eliminating the signal edge slope value affected by Ledge in the technical solution of the present invention includes:

[0037] S1, calculating the first-order derivative of the clock waveform of the collected signal and calculating the average value of the first-order derivative to obtain the slope waveform of the clock waveform of the signal;

[0038] S2, select the two peaks or two valleys of the slope waveform of the signal clock waveform and add them together, and the sum of the obtained values ​​is the slope value of the signal edge at the receiving end of the equivalent chip.

[0039] In step S1, calculating the first-order derivative of the clock waveform of the collected signal is realized through the derivative function of the oscilloscope, and calculating the average value of the first-order derivative of the clock waveform of the collected signal is realized through the average value function of the oscilloscope .

[0...

Embodiment 2

[0050] Such as Figure 4 As shown, a method for eliminating the signal edge slope value affected by Ledge in the technical solution of the present invention includes:

[0051] S1, select the network point on the periphery of the receiving end of the chip as the measurement point, and use the oscilloscope to collect the clock waveform of the signal;

[0052] S2, calculating the first-order derivative of the clock waveform of the collected signal and calculating the average value of the first-order derivative to obtain the slope waveform of the clock waveform of the signal;

[0053] S3, adding two peak values ​​or two valley values ​​of the slope waveform of the signal clock waveform, and the sum of the obtained values ​​is the slope value of the signal edge at the receiving end of the equivalent chip.

[0054] In step S1, the distance between the measuring point and the pin of the receiving end of the chip is 0-1 inch.

[0055] When using the oscilloscope to acquire the clock...

Embodiment 3

[0058] Such as Figure 9 As shown, a device for eliminating the slope value of the signal edge affected by Ledge is characterized in that it includes:

[0059] Obtain the slope waveform module 101, obtain the first-order derivative and average the first-order derivative to the clock waveform of the collected signal, and obtain the slope waveform of the clock waveform of the signal;

[0060] The addition operation module 102 selects two peak values ​​or two valley values ​​of the slope waveform of the signal clock waveform and adds them, and the sum of the obtained values ​​is the slope value of the signal edge at the receiving end of the equivalent chip.

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Abstract

The invention aims to solve the problem that in the prior art, the edge slope value of clock signal testing is influenced by level. The invention provides a method for eliminating a signal edge slopevalue influenced by Ledge. By the adoption of the method, the method is adopted; An existing waveform measurement scheme is continued; the method comprises the following tsteps of collecting waveformsat the periphery of the chip package; calculating a first derivative of the measured waveform and calculating an average value of the first derivative; carrying out addition operation after obtaininga slope waveform; Therefore, calcuating a signal edge slope value equivalent to a chip-packaged Die terminal. The invention further provides a device for eliminating the influence of Ledge on the signal edge slope value, the influence of Ledge generated by measuring the signal waveform edge caused by signal reflection on the accuracy of measured data is eliminated, the precision of clock signal test data is improved, and the signal quality of research and development design is accurately judged and evaluated.

Description

technical field [0001] The invention relates to a method for eliminating signal edge slope values, in particular to a method and device for eliminating signal edge slope values ​​affected by Ledge. Background technique [0002] During the design and development of server products, the CLK clock cycle signal for system interconnection is usually measured by indicators such as the slope of the time domain waveform to determine whether the signal quality meets the system performance evaluation test requirements, and to avoid the edge slope indicators not meeting the requirements. It causes problems such as the failure of the high-speed link transmission signal to collect signal symbols at the receiving end of the chip and the increase of the bit error rate of the effective signal, resulting in the reduction of the effective transmission system bandwidth of the high-speed link and the undetectable status of the system interconnection equipment. Therefore, the quality control of ...

Claims

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Application Information

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IPC IPC(8): G06F17/50G06F17/15G06F17/18
CPCG06F17/15G06F17/18G06F2113/18G06F30/20
Inventor 武宁
Owner ZHENGZHOU YUNHAI INFORMATION TECH CO LTD
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