Robust design method for non-standard input vesa timing sequence

Abstract

The invention provides a robust design method for a non-standard input vesa timing sequence. The method comprises the following steps: firstly, carrying out row counting on a video effective signal DEin an input vesa timing sequence signal, judging whether a frame of data is complete or not, and then, using a synchronous processing mechanism to carry out clock synchronization processing on the video effective signal DE and a video data signal QE; and finally, taking each DE rising edge of the input vesa as a benchmark, adopting a three-section type state machine mechanism, and generating a standard DE effective timing sequence and relative standard HS and VS timing sequences according to a vesa standard timing sequence parameter. According to the method in the invention, the non-standardvesa timing sequence can be converted into a relative standard vesa timing sequence, and the data effective signal and the video data are ensured to meet the vesa timing sequence standard.

Description

technical field [0001] The invention relates to the technical field of video processing, in particular to the conversion of VESA timing, in particular to a robust design method for non-standard input VESA timing. Background technique [0002] At present, pre-distortion technology is generally used in civil aircraft head-up display and other digital head-up display to preprocess the input video image to eliminate the distortion of the optical system. However, in the process of image conversion and processing, since the input VESA timing sequence does not necessarily fully comply with the VESA standard timing sequence, the logic has a great impact on the robustness of the output image by the way the input VESA protocol data is processed. Bad processing methods may lead to abnormal output screen. It is necessary to propose a robust design method for non-standard input VESA timing, and correct the input non-standard timing to ensure the correctness of the VESA timing output to ...

AI Technical Summary

Problems solved by technology

However, in the process of image conversion and processing, because the input VESA timing sequence does not necessarily fully comply with the VESA standard timing sequence, the logic has a great impact on the robustness of the output screen by the way the input VESA protocol data is processed.

Bad processing methods may lead to abnormal output screen

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