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Voltage multiplier circuit for generating positive and negative voltages

A voltage multiplier, negative voltage technology, applied in logic circuits, instruments, electrical components, etc., can solve problems such as large integrated circuit area and occupation

Active Publication Date: 2021-10-26
STMICROELECTRONICS SRL
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Those skilled in the art realize that providing three different isolated PWELL structures would occupy a significant amount of integrated circuit area

Method used

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  • Voltage multiplier circuit for generating positive and negative voltages
  • Voltage multiplier circuit for generating positive and negative voltages
  • Voltage multiplier circuit for generating positive and negative voltages

Examples

Experimental program
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Embodiment Construction

[0034] now refer to Figure 4 , which shows a circuit diagram of the voltage multiplier circuit 200 . The same reference numerals indicate figure 1 the same or similar parts in . Voltage multiplier circuit 200 differs from voltage multiplier circuit 100 in that each n-channel transistor MN1 - MN6 of circuit 200 is formed to share a common body (body) 202 . Another difference is that the source terminals of n-channel MOS transistors MN1 - MN6 are not connected to common body 202 . However, the public subject 202 is not a floating node. Yet another difference is that the circuit 200 also includes a circuit 204 for biasing the common body 202 .

[0035] The bias circuit 204 is formed of a pair of n-channel MOS transistors MN7 and MN8 whose source-drain paths are connected in series between the nodes A and B. More specifically, the drain of transistor MN7 is connected to node A, and the drain of transistor MN8 is connected to node B. The sources of the transistors MN7 and M...

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PUM

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Abstract

Embodiments of the present disclosure relate to voltage multiplier circuits for generating positive and negative voltages. A voltage doubler circuit supports operation in both a positive voltage boost mode to positively boost voltage from a first node to a second node and a negative voltage boost mode to negatively boost voltage from the second node to the first node Boost. The voltage doubler circuit is formed from transistors of the same conductivity type sharing a common body that is not connected to the source of any of the voltage doubler circuit transistors. A bias generator circuit is coupled to receive a first voltage from the first node and a second voltage from the second node. The bias generator circuit operates to apply the lower of the first voltage and the second voltage to the common body.

Description

[0001] priority claim [0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 575692, filed October 23, 2017, the disclosure of which is incorporated herein by reference. technical field [0003] The present invention relates to voltage multiplying (eg, doubling) circuits configured to generate positive and negative voltages. Background technique [0004] refer to figure 1 , which shows a circuit diagram of the voltage multiplier circuit 100 . Circuit 100 includes n-channel MOS transistor MN1 (having a source terminal coupled to node A and a drain terminal coupled to node NA1) and n-channel MOS transistor MN2 (having a source terminal coupled to node A and coupled to node DRAIN terminal of NA2). Transistor MN1 and transistor MN2 are cross-coupled, wherein the gate terminal of transistor MN1 is coupled to the drain terminal of transistor MN2 at node NA2, and the gate terminal of transistor MN2 is coupled to the drain terminal of transistor...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H02M3/07
CPCH02M3/07G05F1/10H03K19/096H02M3/078
Inventor V·拉纳
Owner STMICROELECTRONICS SRL