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A H.264-based Deblocking Filter Hardware Architecture

A technology of deblocking filter and hardware architecture, applied in the field of H.264 hardware architecture

Active Publication Date: 2020-12-11
LONGYAN UNIV
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  • Description
  • Claims
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Problems solved by technology

[0006] For this reason, it is necessary to provide a deblocking filter hardware architecture based on H.264 to solve the problem that the existing H.264 hardware architecture still has a great shortage in the processing of memory cost and operation processing speed

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  • A H.264-based Deblocking Filter Hardware Architecture
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  • A H.264-based Deblocking Filter Hardware Architecture

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Embodiment Construction

[0021] In order to explain in detail the technical content, structural features, achieved goals and effects of the technical solution, the following will be described in detail in conjunction with specific embodiments and accompanying drawings.

[0022] see Figure 1 to Figure 8 , this embodiment provides an H.264-based deblocking filter hardware architecture. Next, the deblocking filter algorithm in H.264 / AVC will be described first, and then the hardware architecture of the present invention will be described, and the experimental results will be given at the end.

[0023] Deblocking filter is to use its algorithm to eliminate the block effect in the picture, and produce a smoother picture. In the block-based H.264 / AVC standard, the source of blockiness is due to the use of 4x4 matrix transformation and block motion compensation. Therefore, it becomes an effective tool for removing blockiness. In theory, the deblocking filter can be independent of the system as post-filte...

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Abstract

The invention discloses a deblocking filter hardware architecture based on H.264. The deblocking filter hardware architecture includes a first memory, second memory, an information storage control module, a deblocking filter module, a first multiplexer, a second multiplexer, a third multiplexer, a fourth multiplexer, and a fifth multiplexer; the information storage control module is connected withthe deblocking filter module; the output end of the deblocking filter module is connected with the input end of the first multiplexer; the input end of the second multiplexer is connected with the input end of the third multiplexer; the output end of the third multiplexer is connected with the first memory; and the output of the second multiplexer is connected to the second memory. Different fromthe prior art, the data storage system has the advantages that data are stored through the double read-write port memories and a new data storage mode, the processing speed is increased, the operation time of the deblocking filter is shortened, and meanwhile the use of a system bus is reduced.

Description

technical field [0001] The present invention relates to the technical field of H.264 hardware architecture, in particular to an H.264-based deblocking filter hardware architecture. Background technique [0002] Today, with the vigorous development of information technology, various multimedia technologies are generally combined with Internet applications, such as video conferencing, video on demand, video surveillance, and so on. Today's network technology is already broadband, but with the increase in the number of users and the requirements for picture quality, the network bandwidth will soon be saturated, so the multimedia audio and video compression technology compresses a large amount of data, so that under the existing storage space, it can Accommodate more multimedia data, thereby reducing the time to transmit data on the Internet. [0003] With the development of video compression to the present, ITU-T (Video Coding Experts Group, VCEG) and ISO / IEC (Moving Picture E...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04N19/86H04N19/423
Inventor 曾宪威庄明学夏至贤张凌卢盛荣谢秀珍李永文吴柏翰
Owner LONGYAN UNIV
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