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Method for automatically generating power-on time sequence program

A power-on sequence and automatic generation technology, applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., can solve the problem of heavy repetitive programming workload for digital logic engineers, different power-on sequence, and heavy repetitive programming workload and other issues to achieve the effect of expanding the scope of use and improving work efficiency

Pending Publication Date: 2019-05-14
SHANDONG CHAOYUE DATA CONTROL ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The present invention aims at the technical problem that the repetitive programming workload of the digital logic engineer is large in the prior art, utilizes the Matlab tool to automatically generate the power-on sequence program: automatically generate the verilog power-on sequence code in the Matlab tool, load it into the CPLD / FPGA, In this way, it can solve the problems of different platforms, different power-on sequences, and heavy repetitive programming workload.

Method used

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  • Method for automatically generating power-on time sequence program

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Embodiment 1

[0020] A method for automatically generating a power-on sequence program, comprising:

[0021] Using table format to make statistics and determine the enabling sequence of the power-on enable signals adapted to the CPU, and the enable interval between the power-on enable signals;

[0022] The Matlab tool reads the content in the table, generates verilog code output according to the information recorded in the table, and generates the corresponding .v file and pin constraint file .qsf;

[0023] Load the .v file and the pin constraint file .qsf into Quartus, then compile and generate a bit file, and finally burn it into the CPU.

Embodiment 2

[0025] A method for automatically generating a power-on sequence program as described in Embodiment 1, the difference is that the method for automatically generating a power-on sequence program further includes counting and determining the abnormal enabling conditions of the CPU in a table format.

Embodiment 3

[0027] A method for automatically generating a power-on sequence program as described in Embodiments 1 and 2, the difference is that the method for automatically generating a power-on sequence program also includes using a table format to make statistics and determine the enabling of the reset signal adapted to the CPU Sequence, the corresponding pin of the reset input signal, and the corresponding pin of the reset output signal.

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Abstract

The invention discloses a method for automatically generating a power-on time sequence program. The method comprises the following steps of: counting and determining an enabling sequence of power-on enabling signals adapting to a CPU and enabling intervals among the power-on enabling signals by utilizing a table format; the Matlab tool reading the content in the table, generates Verilog codes according to the information recorded in the table and outputs the Verilog codes, and generates a corresponding. V file and a corresponding pin constraint file. Qsf; loading the. V file and the pin constraint file. Qsf into Quartz, compiling to generate a bit file, and finally programming the bit file into a CPU. According to the method, when the power-on sequence is changed, a new Verilog program canbe generated only by changing the sequence of the signals in the corresponding table, and the working efficiency is improved. In addition, codes in a Matlab tool program can be changed, a c program or a VHDL program is generated, and the application range of the method is enlarged.

Description

technical field [0001] The invention relates to a method for automatically generating a power-on sequence program, which belongs to the technical field of circuit design control. technical background [0002] In recent years, with the continuous development of my country's electronic industry, domestic CPU has been more and more widely used. The computing platform market shows a trend that domestic CPUs and imported CPUs keep pace with each other. The power-on sequence of domestic CPU is generally realized by CPLD. Different CPU chips have different power-on and enable sequences, which will cause the need to redesign the power-on sequence every time a computer or server is produced using different CPUs, and the repetitive programming workload of digital logic engineers will increase significantly. Contents of the invention [0003] Aiming at the deficiencies of the prior art, the invention provides a method for automatically generating a power-on sequence program. [00...

Claims

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Application Information

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IPC IPC(8): G06F17/50
Inventor 于治楼王培培王慧刘毅枫朱亚征
Owner SHANDONG CHAOYUE DATA CONTROL ELECTRONICS CO LTD