neural network acceleration method based on cooperative processing of multiple FPGAs

Abstract

The invention discloses a neural network acceleration method based on multi-block FPGA cooperative processing, and relates to the field of neural network optimization. Establishment of neural networkacceleration board card, an SOC chip and an FPGA are arranged on the acceleration board card; the SOC chip comprises a ZYNQ chip; the ZYNQ chip is interconnected with each FPGA; A ZYNQ chip is based on the complexity of a network model of a neural network. delay requirements and throughput requirements; decomposing the parameters of the network model according to layers; and dividing the FPGA flowseries according to the hierarchy of parameter decomposition, issuing parameters to the FPGA of the corresponding flow series according to the hierarchy of parameter decomposition, and controlling the FPGA started by each flow series according to the neural network model until the FPGA of which the flow series is the last level completes data processing.

Description

technical field [0001] The invention discloses a neural network acceleration method based on multi-block FPGA cooperative processing, and relates to the field of neural network optimization. Background technique [0002] Neural network (Neural Networks, NN) is a complex network system formed by a large number of simple processing units (called neurons) that are widely connected to each other. It reflects many basic features of human brain function and is a highly complex network. Nonlinear dynamical learning systems. Neural network has large-scale parallelism, distributed storage and processing, self-organization, self-adaptation and self-learning capabilities, and is especially suitable for dealing with imprecise and fuzzy information processing problems that need to consider many factors and conditions at the same time. One layer of the existing neural network model cannot be perfectly implemented in parallel on one FPGA, so the processing performance of the neural networ...

AI Technical Summary

Problems solved by technology

One layer of the existing neural network model cannot be perfectly implemented in parallel on one FPGA, so the processing performance of the neural network is reduced when serial processing is required, and the pipeline layered implementation of multiple FPGAs can greatly improve Processing performance of neural networks

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