Three-dimensional semiconductor device including vertical structures

Abstract

A three-dimensional semiconductor device is provided including a gate electrode disposed on a substrate and having a pad region; a cell vertical structure passing through the gate electrode; a dummy vertical structure passing through the pad region; and a gate contact plug disposed on the pad region. The cell vertical structure includes a cell pad layer disposed on a level higher than that of thegate electrode and a cell channel layer opposing the gate electrode, the dummy vertical structure includes a buffer region formed of a material different from that of the cell pad layer and a dummy channel layer formed of a material the same as that of the cell channel layer, and at least a portion of the buffer region is located on the same plane as at least a portion of the cell pad layer.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2017-0154892 filed in the Korean Intellectual Property Office on November 20, 2017, the disclosure of which is hereby incorporated by reference in its entirety. technical field [0002] The inventive concept relates to a semiconductor device, and more particularly, to a three-dimensional semiconductor device including a vertical structure passing through a gate electrode. Background technique [0003] Semiconductor devices including gate electrodes stacked in a direction perpendicular to the surface of a semiconductor substrate have been developed. For high integration of semiconductor devices, the number of stacked gate electrodes has increased. As described above, as the number of gate electrodes stacked in the direction perpendicular to the surface of the semiconductor substrate increases, the degree of difficulty of the gate formation process gradually increases, and unexpected d...

AI Technical Summary

Problems solved by technology

As described above, as the number of gate electrodes stacked in the direction perpendicular to the surface of the semiconductor substrate increases, the degree of difficulty of the gate formation process gradually increases, and unexpected defects occur

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