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A method and a system for realizing binary parallel addition based on a phase change memory

A technology of phase-change memory and binary addition, which is applied in the field of binary parallel addition based on phase-change memory, and can solve problems such as slow calculation speed

Inactive Publication Date: 2019-06-04
HUAZHONG UNIV OF SCI & TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] Aiming at the defects of the prior art, the purpose of the present invention is to solve the technical problem that the existing calculations using phase change memory are mostly serial calculations and the calculation speed is very slow

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  • A method and a system for realizing binary parallel addition based on a phase change memory

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Embodiment Construction

[0038] In order to make the object, technical solution and advantages of the present invention more clear, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not constitute a conflict with each other.

[0039] Phase change memory has been widely used so far, not only for storage, but also plays an important role in memory computing and neuromorphic computing, among which the polymorphic characteristics of phase change memory play an important role. Therefore, the present invention utilizes the multi-valued characteristic of the phase-change memory to realize two-bit binary parallel addition ...

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Abstract

The invention discloses a method and system for realizing binary parallel addition based on a phase change memory, and the method comprises the steps: a first phase change memory receives a first pulse signal, and converts the first pulse signal into a corresponding first resistance value; The first amplification circuit reads the first resistance value and amplifies the first resistance value toobtain a corresponding first voltage value; The first analog-to-digital conversion circuit converts the first voltage value into first two-bit binary data; The second phase change memory receives thesecond pulse signal and converts the second pulse signal into a corresponding second resistance value; The second amplification circuit reads the second resistance value and amplifies the second resistance value to obtain a corresponding second voltage value; The second analog-to-digital conversion circuit converts the second voltage value into second two-bit binary data; And the decoding circuitis used for carrying out addition operation on the first two-bit binary system and the second two-bit binary system to obtain three-bit binary data and outputting the three-bit binary data. Accordingto the invention, the two-bit binary parallel addition calculation is realized by applying pulses to the phase change memory unit and combining the processing of a subsequent circuit.

Description

technical field [0001] The invention belongs to the technical field of microelectronics, and more specifically relates to a method and system for realizing binary parallel addition based on a phase-change memory. Background technique [0002] Phase-change memory is a non-volatile memory developed by utilizing the characteristics of phase-change materials that can quickly and repeatedly switch between crystalline and amorphous states and that different states have huge property differences. It is expected to replace flash memory as the next-generation mainstream memory . Switching between states is currently mainly achieved by applying pulses. There are two types of operations for phase-change memory cells: SET and RESET. The SET operation is to apply a pulse with a longer duration and medium amplitude to the phase change unit to reduce the crystallization resistance, and the RESET operation is to apply a pulse with a shorter duration and higher amplitude to amorphize the r...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/4091G11C11/56
Inventor 李震张浩胡阳缪向水
Owner HUAZHONG UNIV OF SCI & TECH
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