Packaging substrate manufacturing process, packaging substrate and wafer packaging structure
A technology for packaging substrates and manufacturing processes, which is used in semiconductor/solid-state device manufacturing, electrical components, and electrical solid-state devices. The effect of market demand
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[0041] Below, the present invention will be further described in conjunction with the accompanying drawings and specific implementation methods. It should be noted that, under the premise of not conflicting, the various embodiments described below or the technical features can be combined arbitrarily to form new embodiments. .
[0042] see Figure 1-2 , a packaging substrate manufacturing process S100 disclosed in an embodiment of the present invention is used to manufacture a packaging substrate for wafer packaging. The packaging substrate manufacturing process S100 includes:
[0043] In step S10, the first conductive sheet 10 with the boss 11 on one side and the insulator 20 with the receiving cavity 21 on one side are stacked and pressed together in such a way that the boss 11 is opposite to the receiving cavity 21, and the boss 11 is accommodated in the In the housing cavity 21, the second conductive sheet 30 is stacked and pressed on the side of the insulating member 20 ...
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