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Method for forming semiconductor structure

A manufacturing method, semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of increasing the complexity of processing and manufacturing ICs

Inactive Publication Date: 2019-06-04
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This scaling also increases the complexity of handling and manufacturing ICs, and similar developments in IC processing and manufacturing are required to achieve these advances.

Method used

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  • Method for forming semiconductor structure
  • Method for forming semiconductor structure
  • Method for forming semiconductor structure

Examples

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Embodiment Construction

[0013] The following disclosure provides many different embodiments, or examples, for implementing different features of the presented subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. For example, in the description below, forming a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments in which the first and second features are formed Embodiments where additional features are formed such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat element symbols and / or letters in various examples. This repetition is for brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] In addition, f...

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Abstract

The invention discloses a method for forming a semiconductor structure, and the method includes the steps: forming a metal layer over a substrate; forming a dielectric layer over the metal layer; removing a first portion of the dielectric layer to expose a first portion of the metal layer, while a second portion of the dielectric layer remains on the metal layer; selectively forming a first inhibitor on the second portion of the dielectric layer, while the metal layer is free of coverage by the first inhibitor; and selectively depositing a first hard mask on the exposed first portion of the metal layer, while the first inhibitor is free of coverage by the first hard mask.

Description

technical field [0001] The present disclosure relates to a method for manufacturing a semiconductor structure. Background technique [0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC development, functional density (ie, the number of interconnected elements per die area) has generally increased while geometry size (ie, the smallest component (or wiring) that can be produced using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down also increases the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are required to achieve these advances. Contents of the invention [0003]...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8238H01L21/28
CPCH01L21/3105H01L21/32H01L21/321H01L21/0337H01L21/0228H01L21/31116H01L29/66545H01L29/66795H01L29/401H01L21/76829H01L21/31053H01L21/76826H01L21/3115H01L21/31144H01L21/32051
Inventor 苏嘉伟颜甫庭蔡腾群
Owner TAIWAN SEMICON MFG CO LTD