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Memory device

A memory and memory array technology, applied in static memory, digital memory information, information storage, etc., can solve the problems of increasing manufacturers' research and development costs and consuming a lot of research and development time

Active Publication Date: 2019-06-11
WINBOND ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, memory products with different storage capacities usually require independent development time, unique mask equipment for each memory product, and use of different semiconductor process
In other words, modifying the storage capacity of memory products will consume a lot of research and development time, thereby increasing the research and development costs of manufacturers

Method used

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Embodiment Construction

[0075] figure 1 It is a block diagram illustrating a memory device 100 according to an embodiment of the present invention. The memory device 100 includes a first chip 110 and a second chip 120 . The first chip 110 is adjacent to the second chip 120 , and a scribe line SL is provided between the first chip 110 and the second chip 120 . The first chip 110 mainly includes a first memory array 112 , a first signal buffer 114 and a plurality of first pads 116 . The first chip 110 may further include a peripheral circuit 118 and a first fuse 119 . The second chip 120 mainly includes a second memory array 122 , a second signal buffer 124 and a plurality of second pads 126 . The second chip 120 may further include a peripheral circuit 128 and a second fuse 129 .

[0076]The first signal buffer 114 in the first chip 110 is coupled to the second signal buffer 124 in the second chip 120 through at least one wire 130 . The wire voltage VDD, the ground voltage VSS and many internal s...

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Abstract

The present invention provides a memory device. The memory device includes a first chip and a second chip. The first chip includes a first memory array, a first signal buffer and a plurality of firstpads. The second chip includes a second memory array, a second signal buffer and a plurality of second pads. The second signal buffer is coupled to the first signal buffer by at least one connection wire, and the at least one connection wire passes through a scribe line between the first chip and the second chip. When the scribe line between the first chip and the second chip is not cut, signals are transmitted between the first signal buffer and the second signal buffer via the at least one connection wire, and the first memory array and the second memory array are commonly connected to the first pads and not connected to the second pads.

Description

technical field [0001] The invention relates to a technology of a memory device, in particular to a memory device whose storage capacity is determined by whether the dicing lines between chips are cut. Background technique [0002] Current memory devices are all manufactured by semiconductor process, such as Dynamic Random Access Memory (Dynamic Random Access Memory; DRAM), Static Random Access Memory (Static RAM; SRAM), Flash Memory (Flash Memory) and pseudo-static Random Access Memory (Pseudostatic RAM; PSRAM). These memory devices usually need to provide products with different sizes (ie, different storage capacities) (eg, 8M to 128M), so that consumer electronic devices can be configured according to their needs. [0003] However, memory products with different storage capacities generally require independent development time, unique masking equipment corresponding to each memory product, and use of different semiconductor manufacturing processes. In other words, modif...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C7/10H01L25/065
CPCG11C5/025G11C7/1057G11C5/06G11C7/1084G11C11/4093G11C2211/4066G11C5/14
Inventor 中冈裕司
Owner WINBOND ELECTRONICS CORP