Array substrate and manufacturing method thereof
A technology of an array substrate and a manufacturing method, which is applied in the field of display device manufacturing, can solve problems such as large via hole impedance and easy disconnection of pixel electrodes, and achieve the effect of reducing impedance and avoiding disconnection
Active Publication Date: 2019-06-14
NANJING CEC PANDA FPD TECH CO LTD
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Problems solved by technology
[0004] The purpose of the present invention is to provide an array substrate and its manufacturing method, aiming to solve the problem that the pixel electrode is prone to disconnection at the position of the via hole in the existing process, resulting in excessive impedance of the via hole
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[0031] Below in conjunction with accompanying drawing and specific embodiment, further illustrate the present invention, should be understood that these embodiments are only for illustrating the present invention and are not intended to limit the scope of the present invention, after having read the present invention, those skilled in the art will understand various aspects of the present invention Modifications in equivalent forms all fall within the scope defined by the appended claims of this application.
[0032] The present invention provides an array substrate, the array substrate includes a pixel area located in the middle and a terminal area located at the edge, and the manufacturing method of the array substrate includes the following steps:
[0033] S1: if figure 1 As shown, the first metal is used to form the gate 2 on the pixel area and the terminal area of the glass substrate 1 respectively;
[0034] S2: if figure 2 As shown, a gate insulating layer 3 coverin...
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The invention provides an array base plate and a manufacturing method thereof. The array base plate comprises a pixel region and a terminal region, wherein the pixel region comprises a grid electrode,a grid electrode insulation layer, a metal oxide semiconductor layer, a source electrode, a drain electrode, a first insulation layer, a second insulation layer, a communication electrode, a third insulation layer, a pixel electrode and a fourth through hole, wherein the pixel electrode is conducted with the drain electrode through the fourth through hole; the terminal region comprises a grid electrode, a grid electrode insulation layer, a metal oxide semiconductor layer, a source electrode, a drain electrode, a first insulation layer, a second insulation layer, a third insulation layer, a pixel electrode and a fifth through hole; and the pixel electrode is conducted with the grid electrode through the fifth through hole. Photoresist, the third insulation layer and the first insulation layer are etched at the same time through the pixel region; the third insulation layer, the first insulation layer and the grid insulation layer are etched at the same time through the terminal region;the over etching influence of the pixel region on the first insulation layer, the second insulation layer and the surface of the drain electrode can be reduced; and the impedance in the through holesis reduced.
Description
technical field [0001] The present invention relates to the technical field of display device manufacturing, in particular to an array substrate and a manufacturing method thereof. Background technique [0002] The liquid crystal display device is the most widely used flat panel display device at present. The liquid crystal display panel includes an array substrate and a color filter substrate oppositely arranged. The processes include masking, exposure, development, etching, and stripping. In order to reduce the price of liquid crystal display panels and improve the yield of products, technicians are working hard to reduce the number of patterning processes. [0003] Usually, the BCE process generally adopts an 8-pass photomask process. By using MTM (Multi-Tones Mask, multi-tone mask) technology, the original 8-pass photomask can be reduced to a 6-pass photomask process, but the terminal area in the 6-pass photomask process uses The first inorganic insulating layer, the se...
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Login to View More IPC IPC(8): H01L21/77H01L27/12
Inventor 郑帅简锦诚胡威威董波高威杨帆
Owner NANJING CEC PANDA FPD TECH CO LTD