A user-defined floating-point number and a calculation method and a hardware structure thereof

A calculation method and floating-point number technology, which is applied in the field of convolutional neural network, can solve the problems of inadaptability and high power consumption data representation, and achieve the effects of simplifying calculation, expanding parallelism, throughput and calculation density

Inactive Publication Date: 2019-06-18
SHANGHAI JIAO TONG UNIV
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AI Technical Summary

Problems solved by technology

Dynamic fixed-point numbers can simplify calculations, but due to the limited range of decimal point positions, they are usually only suitable for the reasoning process of CNNs, and cannot be adapted to the training of large-scale CNNs
In the latest research on floating point numbers, the mini floating po

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  • A user-defined floating-point number and a calculation method and a hardware structure thereof
  • A user-defined floating-point number and a calculation method and a hardware structure thereof
  • A user-defined floating-point number and a calculation method and a hardware structure thereof

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[0040] The present invention will be described in detail below in conjunction with specific embodiments. The following examples will help those skilled in the art to further understand the present invention, but do not limit the present invention in any form. It should be noted that for those of ordinary skill in the art, several changes and improvements can be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0041] A custom floating-point number provided according to the present invention is composed of an integer part and a shared exponent. The integer part is composed of 1 sign bit and Z-1 mantissa bit. Z represents the number of digits of the integer part, and the shared exponent is 8 bits. The shared exponent has the same bit width as a single-precision floating point number.

[0042] Specifically, when the original data is quantized from a single-precision floating-point format to a custom...

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Abstract

The invention provides a user-defined floating-point number with a shared index. A 32-bit floating-point based neural network model to 8-bit, which greatly reduces the size of the model while reducingthe computational complexity. In user-defined floating-point operations, integer multiplication and addition are used. Compared with 32-bit floating point multiplication, the multiplication of user-defined floating point numbers saves 17 times of the energy consumption, 30 times of the chip area; the addition operation saves 28 times of the energy consumption and 116 times of the chip area.; in the network parameters of the full connection layer, the memory bandwidth required by the data transmitted to the off-chip memory is reduced by four times. The user-defined floating-point number is helpful for maintaining parameters over four times in the on-chip buffer. In the hardware implementation, combined with the 8-bit user-defined floating-point number and multiplier package structure, theoperation speed and throughput of the entire neural network are increased on the operation unit CU..

Description

technical field [0001] The present invention relates to the technical field of convolutional neural network, specifically, relate to a kind of self-defined floating-point number and its calculation method and hardware structure, especially design relates to a kind of based on self-defined floating-point and shared exponent, in FPGA convolutional neural network The multiplier package structure. Background technique [0002] In recent research on convolutional neural networks (CNNs), most models pay little attention to their complexity in order to maximize accuracy. For example, in modern deep CNN models, such as AlexNet, GoogleNet, and ResNet, all require millions of parameters and billions of arithmetic operations, the extremely high computational complexity and massive resource consumption hinder the development of embedded devices. accomplish. [0003] Reducing the representation precision of data is a common way to speed up training and reduce memory bandwidth. In term...

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Application Information

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IPC IPC(8): G06F7/485G06F7/487
Inventor 张煜祺刘功申
Owner SHANGHAI JIAO TONG UNIV
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