Physical vapor deposition process for semiconductor interconnection structures

Abstract

The present invention provides methods for forming a conductive fill material (e.g., a conductive feature) by a physical vapor deposition (PVD) process. In one embodiment, a method of forming a conductive fill material on a substrate includes maintaining a first substrate temperature at a first range for a first period of time while forming a pre-layer of a conductive fill material on a substrate,providing a thermal energy to the substrate to maintain the substrate at a second substrate temperature at a second range for a second period of time, with the second substrate temperature being higher than the first substrate temperature; and continuously providing the thermal energy to the substrate to maintain the substrate a third substrate temperature at a third range for a third period of time to form a bulk layer of the conductive fill material on the substrate. Embodiments of the invention relate to a physical vapor deposition process used for a semiconductor interconnection structure.

Description

technical field [0001] Embodiments of the present invention relate to physical vapor deposition processes for semiconductor interconnect structures. Background technique [0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (eg, the number of interconnected devices per chip area) has generally increased, while geometry size (eg, the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. However, scaling down also creates challenges that may not have been present with the larger geometries of the previous generation. Inaccurate and inadequate control of th...

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Problems solved by technology

However, scaling down also creates challenges that may not have been present with the larger geometries of the previous generation

Inaccurate and improper control of deposition and patterning processes during metallized interconnect fabrication can severely deteriorate the electrical performance of device structures

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