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Delay control circuits

A delay control and circuit technology, applied in the direction of electrical components, impedance networks, pulse processing, etc., can solve the problems of delay line circuit delay error, duty cycle change, delay error increase, etc.

Inactive Publication Date: 2019-07-12
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] However, delay line circuits may produce delay errors when PVT variations occur due to external factors
The delay error can increase exponentially as the delay time generated by the delay line gets longer
Also, when the signal passes through the delay line at a skewed corner, the duty cycle may change

Method used

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Examples

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Embodiment Construction

[0027] Figure 1A and Figure 1B is an example circuit diagram used to illustrate the step delay unit. figure 2 is an example timing diagram illustrating the voltage at each node of the step delay unit when the power supply noise is relatively small. image 3 is an example timing diagram illustrating the voltage of each node of the step delay unit when the power supply noise is relatively large. Figure 4 is a graph showing the magnitude of the delay error versus the average value of the slope of the second signal P2.

[0028] refer to Figure 1A and Figure 1B , the step delay unit 100 may include an input inverter 110, an output inverter 120, and a variable capacitor CC.

[0029] The input stage of the input inverter 110 may be connected to the input node I. The output stage of the input inverter 110 may be connected to a delay node S. The input stage of the output inverter 120 may be connected to the delay node S. The output stage of the output inverter 120 may be co...

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Abstract

A delay control circuit includes: a first step delay cell including a first switch having a first end connected to a first node, and a first capacitor connected to a second end of the first switch; asecond step delay cell including a second switch having a first end connected to a second node, and a second capacitor connected to a second end of the second switch; and a first inverter configured to couple an output signal of the first step delay cell to an input of the second step delay cell, wherein the first switch and the second switch are turned on and off by a same control signal.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to Korean Patent Application No. 10-2017-0174953 filed with the Korean Intellectual Property Office on December 19, 2017, the disclosure of which is hereby incorporated by reference in its entirety. technical field [0003] Example embodiments provided herein relate to a delay control circuit, and more particularly, to a delay control circuit in which sensitivity to process, voltage, and temperature (PVT) variations is low and duty cycle is maintained. Background technique [0004] Clock accuracy is very important in many areas of digital systems. In particular, it is necessary to synchronize the clock received from the outside with the internal clock. Also, the performance of a digital system can be affected by how accurately the duty cycle is controlled. However, since quantization errors occur due to the characteristics of digital systems, improvement of clock accuracy has become i...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K5/133
CPCH03K5/133H03K5/131H03K5/135H03K5/14H03K2005/00071H03K5/1565H03H11/265
Inventor 李信泳蔡官烨
Owner SAMSUNG ELECTRONICS CO LTD