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Digital signal processing circuit capable of resisting ground and power rebound noise

A digital signal processing and circuit technology, applied to logic circuits with logic functions, logic circuits, electrical components, etc., can solve problems such as inability to resist negative pulse bounce noise, improve signal processing accuracy, achieve low cost, and high performance Stable and reliable effect

Pending Publication Date: 2019-07-23
SUZHOU KAIWEITE SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

So the existing noise canceling circuit cannot resist the negative pulse bounce noise on the ground

Method used

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  • Digital signal processing circuit capable of resisting ground and power rebound noise
  • Digital signal processing circuit capable of resisting ground and power rebound noise
  • Digital signal processing circuit capable of resisting ground and power rebound noise

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Embodiment Construction

[0019] In order to deepen the understanding and recognition of the present invention, the present invention will be further described and introduced below in conjunction with the accompanying drawings.

[0020] Such as Figure 4 As shown, it is a digital signal processing circuit against ground and power supply bounce noise given by a preferred embodiment of the present invention, including a first current source Id1, a second current source Id2, a first PMOS transistor P0, and a first NMOS transistor N0 , capacitor C1, second PMOS transistor P1, second NMOS transistor N1, third PMOS transistor P2, fourth PMOS transistor P3, fifth PMOS transistor P4, third NMOS transistor N2, fourth NMOS transistor N3, fifth NMOS transistor N4, an inverter and a voltage locking circuit, the input end of the first current source Id1 is connected to the power supply, the output end of the first current source Id1 is connected to the source of the first PMOS transistor P0, the first PMOS transist...

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PUM

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Abstract

The invention relates to a digital signal processing circuit capable of resisting ground and power rebound noise. The circuit comprises a first current source, a second current source, a first PMOS transistor, a first NMOS transistor, a capacitor, a second PMOS transistor, a second NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a third NMOS transistor,a fourth NMOS transistor, a fifth NMOS transistor, a phase inverter and a voltage locking circuit. The input end of the inverter is connected with the signal input end, the output end of the inverteris connected with the first input end of the voltage locking circuit, the second input end of the voltage locking circuit is connected with the signal output end, and the output end of the voltage locking circuit is connected with the second voltage detection point. The voltage locking circuit can lock the voltage of the second voltage detection point; the circuit not only can eliminate channel transmission noise transmitted from the signal input end, but also can effectively resist rebound noise of positive and negative level pulses generated on a ground wire and a power line, and is low incircuit cost and stable and reliable in performance.

Description

technical field [0001] The invention relates to the technical field of digital signal processing circuits, in particular to a digital signal processing circuit that can resist ground and power supply bounce noise. Background technique [0002] At present, in the design process of digital integrated circuits, the transmission and processing of digital signals are completed through the "1" represented by the high level and the "0" represented by the low level, and the noise in the circuit may enter the signal transmission process , resulting in an erroneous state of the digital signal, so a processing circuit that resists noise needs to be added to the circuit. [0003] Such as figure 1 As shown, it is a commonly used digital signal processing circuit that is resistant to noise. The signal waveforms of each node of the circuit are as follows figure 2 As shown, when the input signal (IN) inputs a rising edge, the current source Id2 will slowly discharge the capacitor at poin...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/094H03K19/20
CPCH03K19/094H03K19/20
Inventor 张胜谭在超丁国华罗寅
Owner SUZHOU KAIWEITE SEMICON
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