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DDR-based high-speed multi-user queue manager and DDR-based high-speed multi-user queue management method

A queue management and multi-user technology, applied in the field of electronic circuits, can solve the problems that read and write operations cannot be performed simultaneously, affect the throughput rate of the queue manager, and the bandwidth utilization rate is not high, so as to ensure the utilization rate of storage resources and improve the utilization rate of bandwidth , Avoid the effect of reading and writing conflicts

Active Publication Date: 2019-07-26
ARMY ENG UNIV OF PLA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, because this method adopts a serial operation mode, the read and write operations cannot be performed at the same time, and the corresponding queue status must be updated after the write or read operation is completed, that is, the data is written to the DDR, or the data is read from the DDR. , and then continue to the next operation; in the process of querying and updating the queue status, the DDR bus is in an idle state, and its bandwidth utilization is not high, which seriously affects the throughput of the entire queue manager

Method used

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  • DDR-based high-speed multi-user queue manager and DDR-based high-speed multi-user queue management method

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Embodiment

[0065] combine figure 1 , the high-speed multi-user queue manager based on DDR of the present invention comprises a write operation module, a read operation module, a DDR interface module and a DDR memory;

[0066] The write operation module is configured to process a write request for a specific queue;

[0067] The read operation module is configured to process a read request for a specific queue;

[0068] The DDR interface module is used to store the data in the buffer of the write operation module to a specified location in the DDR memory, and temporarily store the data in the DDR memory to the internal buffer of the read operation module, and update the write operation module Internal queue status information.

[0069] Further, the write operation module includes first to fourth RAMs, a first data FIFO and a first pointer FIFO;

[0070] The first to fourth RAMs are respectively used to store and manage the first address (head_ram), tail address (tail_ram), write pointer...

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Abstract

The invention discloses a DDR-based high-speed multi-user queue manager and a DDR-based high-speed multi-user queue management method. The queue manager comprises a write operation module, a read operation module, a DDR interface module and a DDR memory. The method comprises the following steps: for a multi-user queue manager in high-performance network equipment, adopting a management mode of separating write operation from read operation, and deploying the write operation and the read operation in different modules; wherein the write operation module and the read operation module respectively maintain respective queue state information, and the two queue state information is synchronously updated through the DDR interface module; and respectively providing the write operation module andthe read operation module with a built-in buffer area for caching data to be written into the DDR memory or data read from the DDR memory. Smooth and reliable management of the multi-user queue is realized, and the throughput of the whole queue structure is improved.

Description

technical field [0001] The invention relates to the technical field of electronic circuits, in particular to a DDR-based high-speed multi-user queue manager and its method. Background technique [0002] In high-speed network equipment, the queue manager needs to use an off-chip large-capacity storage such as DDR as a data buffer to implement storage management for a large number of queues. The length of each queue in the queue manager can be statically divided according to requirements, or dynamically divided based on the linked list structure, so as to effectively manage multiple logical queues under the premise of fully utilizing the storage capacity. [0003] The core circuit of the traditional multi-queue manager is implemented by a single state machine. The read and write operations coexist in the same module, and the two share all the queue status information. The specific operation process is: first generate a read and write operation request, and query according to t...

Claims

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Application Information

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IPC IPC(8): G06F3/06
CPCG06F3/061G06F3/0656G06F3/0659G06F3/067
Inventor 乔庐峰陈庆华孙明乾杨健邹仕祥
Owner ARMY ENG UNIV OF PLA
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