3D memory device and manufacturing method thereof

Abstract

The application discloses a 3D storage device and a manufacturing method thereof. The manufacturing method includes: forming a first buffer layer on the stacked structure; forming at least one set of sacrificial stacks on the first buffer layer, each set of sacrificial stacks including a first mask layer and a mask located on the first mask layer A second buffer layer; forming a second mask layer on the sacrificial stack; forming a filling layer covering the second mask layer and the cutting area; annealing the filling layer; grinding the filling layer, and stopping at the second mask layer ; removing the second mask layer to expose the sacrificial stack; simultaneously grinding the second buffer layer and a portion of the fill layer, stopping at the first mask layer; removing the first mask layer; and grinding the fill layer, stopping at the first The buffer layer. The manufacturing method not only repairs the height difference between the device region and the cutting region caused by the annealing step, but also repairs the height difference caused by the uneven deposition of the filling layer, so that the surface of the 3D storage device is more flat.

Description

technical field [0001] The present invention relates to memory technology, and more specifically, to a 3D memory device and a manufacturing method thereof. Background technique [0002] The improvement of the storage density of the memory device is closely related to the progress of the semiconductor manufacturing process. As the feature size of the semiconductor manufacturing process becomes smaller and smaller, the storage density of the memory device becomes higher and higher. In order to further increase storage density, memory devices with a three-dimensional structure (ie, 3D memory devices) have been developed. A 3D memory device includes a plurality of memory cells stacked in a vertical direction, which can double the integration level on a wafer per unit area and reduce the cost. [0003] Existing 3D memory devices are mainly used as non-volatile flash memory. The two main non-volatile flash memory technologies use NAND and NOR structures, respectively. Compared...

AI Technical Summary

Problems solved by technology

In the array planarization (Array Planarization, APL) process, annealing the dielectric layer will cause the wafer to have a high bow (bow), so that there is a large height difference between the device area and the cutting area, thereby affecting the subsequent mask. form

In addition, the thicker dielectric layer itself will also have the problem of unevenness during deposition, resulting in a large height difference between the dielectric layers in different regions during deposition

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