Subsampled phase detector circuit and method of subsampled bang bang phase detector

Abstract

The invention discloses a sub-sample phase detector circuit and a method of a sub-sample bang bang phase detector. A system and method for a sub-sampling phase detector circuit includes a bang bang phase detector (BBPD), an UP rolling counter connected to an UP output of the BBPD, and a DOWN rolling counter connected to a DOWN output of the BBPD. The charge pump is connected to the UP rolling counter and the DOWN rolling counter, and is configured to receive the decimated UP signal from the UP rolling counter and the decimated DOWN signal from the DOWN rolling counter. The charge pump is further configured to provide a control voltage based on the received decimated UP signal and decimated DOWN signal.

Description

[0001] Cross References to Related Applications [0002] This application claims priority and benefit to U.S. Provisional Patent Application No. 62 / 641,911, filed March 12, 2018, the contents of which are hereby incorporated by reference in their entirety. Background technique [0003] Some embodiments of the present disclosure relate generally to bang bang phase detectors in analog clock data recovery (CDR). [0004] A serial link includes a transmitter connected to a receiver via a channel. The receiver typically includes circuitry configured to generate a clock that is phase aligned with the incoming data. [0005] Figure 1 depicts a prior art CDR circuit configured to align a locally generated clock with an incoming data signal. [0006] Referring to FIG. 1 , a prior art CDR system 100 includes a data and span slicer 110 that samples input data and provides the data to a bangbang phase detector 120 . The bang bang phase detector 120 determines whether the phase of the c...

AI Technical Summary

Problems solved by technology

State-of-the-art methods of decimating the output of a bang bang phase detector typically discard information

Images