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Method and system for systematic adjustments in high-speed nonstandard fet circuits

A circuit system and circuit technology, applied in the field of data communication

Inactive Publication Date: 2005-03-23
QANTEC COMM
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] (004) Although the potential of these non-standard FET ICs approaches their base-speed performance in practical circuits for such ultra-high-speed applications, a balanced system design methodology must be developed

Method used

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  • Method and system for systematic adjustments in high-speed nonstandard fet circuits
  • Method and system for systematic adjustments in high-speed nonstandard fet circuits
  • Method and system for systematic adjustments in high-speed nonstandard fet circuits

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Embodiment Construction

[0022] (009) In the following detailed description of the invention, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the invention. The detailed description is given extensively in terms of logic blocks and other symbolic representations that operate, directly or indirectly, like signal processing devices coupled to networks.

[0023] These instructions and representations are the means used by those skilled in the art to most effectively convey the substance of their work to others skilled in the art.

[0024] (010) Reference herein to "one embodiment" or an "embodiment" means that a particular feature, structure, or characteristic descr...

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Abstract

A method of designing an electronic circuit system with multiple Field Effect Transistors (FETs) made by a variety of nonstandard industrial processes is presented. With this method, the circuit parameters of the various components of the individual functional building blocks of the circuit system are systematically adjusted to minimize the many deteriorating effects resulting from system-level interactions among these functional building blocks. In one embodiment, the method is applied to a Silicon On Insulator (SOI) CMOS IC that is a Divide-by-16 divider where the functional building blocks are four Divide-by-2 dividers. The resulting drastic improvement of output signal ripple from each divider stage is graphically presented. In another embodiment, the method is applied to another SOI CMOS IC that is a Bang Bang Phase Detector where the functional building blocks are three Master Slave D-Type Flip Flops. The resulting drastic improvement of output signal ripple is also graphically presented.

Description

Background of the invention [0001] (002) The present invention relates generally to the field of data communications. In more detail, the present invention relates to a general design methodology for a new family of field effect transistor (FET) integrated circuits (ICs) manufactured using non-standard processes. Therefore, its direct application includes various subsystems and system functions: such as master-slave D-type flip-flop (MS-DFF), divider, Bang Bang phase detector ( BBPD), frequency detection (FD), phase and frequency detection (PFD), voltage-controlled oscillator (VCO) and phase-locked loop (PLL). [0002] (003) Optical fiber has been used for some time now in voice and data communications due to its high bandwidth and its excellent signal quality due to its resistance to electromagnetic interference. Intrinsic optical data rates from a modulated single-mode laser beam through fiber optics are expected to be better than 1000Gbit / sec. However, without reaching a...

Claims

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Application Information

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IPC IPC(8): G06F17/50H01L29/06H03K19/00
CPCG06F17/5045H03K19/018528G06F30/30
Inventor J·C·董张明皓
Owner QANTEC COMM
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