A Bang-bang Phase Detector Applied in Subrate Clock Data Recovery Circuit

Abstract

The invention discloses a Bang-Bang phase discriminator for a sub-rate clock data recovery circuit. The Bang-Bang phase discriminator comprises multiple data samplers, an edge sampler, multiple data synchronizers, an edge synchronizer, and two XOR gates. The two XOR gates receive a retimed edge signal and a retimed data signal and then generate a leading voltage signal including phase difference information between a sampling clock and input data and a lagging voltage signal including phase difference information between the sampling clock and input data. The number of multiphase clocks required by the 1 / N rate Bang-Bang phase discriminator is decreased so that the jitter performance of the whole clock data recovery circuit is improved, and the operating frequencies of modules, such as the Bang-Bang phase discriminator and a voltage-controlled oscillator, in the clock recovery circuit are reduced.

Description

technical field [0001] The invention relates to the technical field of high-speed serial communication and high-speed analog integrated circuit, in particular to a Bang-Bang phase detector applied to a sub-rate clock data recovery circuit. Background technique [0002] Bang-Bang Phase Detector (BBPD), as an important module in Clock Data Recovery (CDR), is widely used in various high-speed serial communications, such as in Synchronous Optical Network (SONET), Passive Optical Network (PON) ) and 10 Gigabit Ethernet (10GbE) and other high-speed serial communication systems at the receiver side. The main function of the Bang-Bang phase detector is to detect the phase difference information between the input data and the sampling clock signal, and retiming to restore the data signal, but with the continuous increase of the data transmission rate (which has reached 10Gbps or even Higher), it is difficult for the receiving end to design a high-performance voltage-controlled oscil...

AI Technical Summary

Problems solved by technology

Traditional 1 / 4 rate Bang-Bang phase detector structure, such as figure 1 As shown, this structure avoids the maximum frequency limit that the on-chip clock can achieve; however, the clock data recovery circuit of this structure needs to provide 8 samplers, 8 synchronizers and 9 clock signals to sample and synchronize the input data / edge signals , an additional majority voter circuit is required, which undoubtedly increases additional area, power consumption and design complexity. More importantly, too many multi-phase sampling clocks can easily cause phase deviations, which in turn affect the entire 1 / Jitter Performance of 4-Rate Architecture Clock Data Recovery Circuit

Images