Programming voltage generation circuit of double-separation-gate memory unit

Abstract

The invention discloses a programming voltage generation circuit of a double-separation-gate memory unit, which provides programming signals for programming of the memory unit, and the programming signals comprise word line signals, bit line signals, first control gate line signals and second control gate line signals, wherein the word line is in signal connection with the surface of the channel region at the bottom of the second control gate structure to form a channel, the first control gate line is in signal connection with the second control gate line and enables a channel to be formed onthe surface of the channel region at the bottom of the first gate structure, and the third control gate line is in signal connection with the third control gate line and enables a channel to be formedon the surface of the channel region at the bottom of the third gate structure, the word line signal is composed of multiple paths of input voltages Vb including Vb0-Vbm, and the average value of thevoltages Vb0-Vbm is obtained through a voltage averaging circuit to serve as word line programming voltage, so that the word line programming voltage tracks the threshold voltage of a memory unit, and a programming window is increased.

Description

technical field [0001] The invention relates to the field of design and manufacture of semiconductor devices, in particular to a programming voltage generation circuit for a double-separated-gate memory unit. Background technique [0002] like figure 1 Shown is a structure diagram of a memory cell of the existing double split gate memory, and the memory cell includes: a first gate structure, a second gate structure, a third gate structure, a source region and a drain region. [0003] The first gate structure is located on the far left, consisting of a gate dielectric layer formed on the surface of the semiconductor substrate (the gate dielectric layer is the blank area between the square frames (gates), a floating gate (Floating Gate, FG), The gate dielectric layer and the polysilicon control gate are stacked, and the polysilicon control gate is led out to form a control gate line CG0. The source region and the drain region are usually N+ doped, the source region and the d...

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Problems solved by technology

[0015] The disadvantage of the above-mentioned circuit structure is that the change of the threshold voltage of the memory cell due to the process difference between the PT corner and the die cannot be tracked, which will affect the programming window, resulting in a smaller programming window of the memory cell, resulting in a device failure. Performance drop

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