Wafer package map error correction system solution

Abstract

The invention discloses a solution to a wafer packaging map error correction system. A substrate map is added to the SMT station equipment, and the coordinates of each product on the substrate corresponding to the wafer map are recorded; when it is found that the map is incorrectly matched, bad chips are mixed in. At the same time, you only need to input the offset information + substrate map into the error correction system. Through the calculation of the error correction system, it can automatically display which products on the substrate are defective, and then according to the system prompt information, the defective products will be deducted to avoid further damage to the products. Loss.

Description

technical field [0001] The invention relates to a solution to an error correction system for a wafer package map. Background technique [0002] In the diebonding station of chip packaging, when picking up the chip, the placement machine will pick up the wafer according to the map (wafermapping) tested before the wafer leaves the factory. It is guaranteed that only good products will be taken, and bad products will not be picked up. , which requires the machine to match the actual wafer with the map before picking up the crystal. If the two match incorrectly, it will cause bad products to be produced as good ones, and subsequent tests will be defective. [0003] With the development of multi-layer chip stacking technology, more and more chips are stacked together. Multi-layer chip packaging requires multiple placements, and each placement requires matching of wafers and maps. , and as long as one of the matching errors cannot be found in time, the loss will be huge. For exam...

AI Technical Summary

Problems solved by technology

[0006] The solution of the wafer packaging map error correction system of the present invention is aimed at the chip packaging placement station. When the chip is captured, the bad product caused by the pairing of the actual wafer and the map is produced as a good product, resulting in a defective rate of chip testing. problem, the following solutions are proposed:

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