Comparator clock generation circuit of SAR ADC and high-speed successive approximation type analog-to-digital converter

Abstract

The invention provides a comparator clock generation circuit of an SAR ADC. The comparator clock generation circuit comprises a signal input module, a time delay module, an adjusting module and a clock module. The signal input module is used for providing a first control signal Clke for the adjusting module; the time delay module is used for generating a third control signal Clki according to a sampling signal Clkin of the SAR ADC and a second control signal Clkinn, wherein the second control signal Clkinn is an inverting signal of the sampling signal Clkin; the clock module is used for generating a clock signal Clko (i) according to the second control signal Clkinn and the third control signal Clki; the adjusting module generates a fourth control signal Clk according to the first controlinput signal Clke and the clock signal Clko (i), and the fourth control signal Clk serves as an input signal of the comparator. When the SAR ADC is in a high-speed sampling state, the comparison clockof the comparator generated by the comparator clock generation circuit also works in a high-frequency state, and the requirement of the SAR ADC for high-speed conversion is met.

Description

technical field [0001] The invention belongs to the technical field of analog or digital-analog mixed integrated circuits, and relates to a comparator clock generation circuit for SAR ADC and a high-speed successive approximation analog-to-digital converter. Background technique [0002] In recent years, with the further improvement of the performance index of the analog-to-digital converter, especially with the continuous development of the integrated circuit process technology, the research on the high-speed successive approximation analog-to-digital converter (SAR ADC) has become more and more in-depth. With the continuous evolution of integrated circuit manufacturing processes, the design of high-gain operational amplifiers has become more and more difficult. Since no operational amplifiers are required, SAR ADCs have a natural advantage of low power consumption, especially at nanoscale process nodes. SAR ADCs The speed has been greatly improved. Therefore, high-speed S...

AI Technical Summary

Problems solved by technology

However, after the last successive approximation process is completed and before the next sampling starts, the waiting time increases significantly

The increase of the waiting time does not improve the accuracy of the SAR ADC, therefore, the traditional asynchronous SAR ADC will waste a lot of time in the case of low-speed sampling

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