Chip rewiring structure and preparation method thereof

Abstract

The invention provides a chip rewiring structure and a preparation method thereof. The chip rewiring structure includes a chip body, a first wiring layer and a second wiring layer connected to the chip body, and a first wiring layer is arranged on the surface of the chip body. Pins and second pins, the chip rewiring structure also includes a dielectric layer arranged on the surface of the chip body, the dielectric layer is recessed downwards to form a first window, a second window and a connection with the first window groove, the first window and the second window correspond to the first pin and the second pin respectively, and the first wiring layer extends along the groove and is connected to the first pin The second wiring layer is disposed above the dielectric layer and communicates with the second pin. In the present application, the first wiring layer and the second wiring layer are dislocated along the height direction through the dielectric layer provided with grooves, which overcomes the size limitation of the existing rewiring process, can increase the rewiring density, and reduce the risk of short circuit.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a chip rewiring structure and a preparation method thereof. Background technique [0002] With the continuous development of the semiconductor industry, the requirements for the integration density of chips involved in various electronic products are also increasing. During the packaging process, the pins formed by the top metal on the surface of the chip usually need to be redistributed and connected to the corresponding conductive bumps by using a redistribution layer (RDL, redistribution layer). The line size of the RDL itself and the gaps between different RDLs are limited by the actual process capability and cannot be continuously reduced, that is to say, the wiring density of the RDL on the chip surface cannot be increased without limit. [0003] Under such circumstances, the industry usually adopts multi-layer wiring method for RDL preparation, that is...

AI Technical Summary

Problems solved by technology

The above scheme needs to re-prepare the metal seed layer above the dielectric layer, and etch and remove the redundant metal seed layer after the corresponding rewiring layer is prepared. The process is more complicated.

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