Data splitting structure and method and on-chip implementation thereof
A data and wide data technology, applied in the field of data splitting scheme, structure and system-on-chip, can solve the problem of not being able to deal with the loss of reading efficiency well, and achieve high data splitting efficiency, less hardware logic, and regular design Effect
Active Publication Date: 2019-12-10
XILINX INC
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Existing data splitting schemes are mostly based on direct splitting of input data, which usually cannot handle the reading efficiency loss caused by the difference between input bit width and output bit width.
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[0036] Preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
[0037] Data splitting and conversion is a very common requirement in hardware architecture, and the conversion efficiency is directly related to the operating efficiency of the entire hardware system. Especially for high-bandwidth systems such as neural network computing platforms, the impact of data conversion on efficiency is more obvious.
[0038] A common application scenario for data splitting and transformation is a system-on-chip. A...
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The invention provides a data splitting structure and method and on-chip implementation thereof. The data splitting structure is used for splitting input M-bit-width data into N-bit-width data to be output, N is smaller than or equal to M. The data splitting structure comprises two cache registers with the width of M, and the M-bit-width data being sent in from one cache register and read out fromone cache register with the N-bit-width; and a pointer register used for storing a pointer indicating the starting point of the N-bit-width data to be read currently. When the position of the pointerindicates that one cache register does not include the unread data at the next clock beat, new M-bit-width data is sent to one cache register. Therefore, a new N-bit-width data is read out from the two cache registers at each clock beat, so as to ensure the data output with the highest efficiency. The data splitting scheme provided by the invention is especially suitable for a high-bandwidth system with important data conversion efficiency, such as a neural network computing platform.
Description
technical field [0001] The invention relates to the field of hardware architecture, in particular to a data splitting scheme, a structure using the scheme and an on-chip system. Background technique [0002] Data splitting and conversion is a very common requirement in hardware architecture, and the conversion efficiency is directly related to the operating efficiency of the entire hardware system. Especially for high-bandwidth systems such as neural network computing platforms, the impact of data conversion on efficiency is more obvious. Existing data splitting schemes are mostly based on direct splitting of input data, which usually cannot well deal with the loss of reading efficiency caused by the difference between input bit width and output bit width. [0003] Therefore, there is still a need for a related scheme capable of optimizing data splitting operations. Contents of the invention [0004] In order to solve at least one of the above-mentioned problems, the pre...
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IPC IPC(8): G06F9/30
CPCG06F9/30098
Inventor 王俊斌隋凌志方绍峡于谦单羿
Owner XILINX INC