Configurable image data caching system based on FPGA and DDR3 SDRAM

Abstract

The invention discloses a configurable image data caching system based on an FPGA and a DDR3SDRAM. The system comprises an external storage module, a storage control module, a first cache module, a second cache module and a cache control module, and video image data and clock signals are written into the first cache module from the cache control module for first-stage caching; the storage controlmodule controls to read the data from the first cache module and store the data in an external storage module; then the storage control module controls to read the stored data from the external storage module, and writes the data into the second cache module for second-stage caching; then, the cache control module controls to read the data from the second cache module to the cache control module,the cache control module adjusts the image data and generates corresponding read effective signals, and the configuration data are output to the outside; according to the invention, larger data transmission can be cached, and the effects of real-time performance and stability of data transmission are achieved; and the packaged system only has a few ports, so that the configuration is more convenient.

Description

technical field [0001] The invention relates to the technical field of data storage and image transmission, in particular to a configurable image data cache system based on FPGA and DDR3 SDRAM. Background technique [0002] At present, the development of video image technology is getting faster and faster, the resolution of images is getting higher and higher, and the use of high frame rate images is becoming more and more frequent. In order to achieve real-time effects, we need to cache the collected data , and they require larger and larger cache capacities. Therefore, the requirements for high-speed, large-capacity, and real-time processing of high-resolution, high-frame-rate image data are getting higher and higher. Especially in data caching technology, in the case of occupying valuable memory, data caching provides fast access to data and speeds up the response speed. But a cache that is too small will cause additional overhead that is not beneficial, and a cache tha...

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to provide a configurable image data buffer system based on a FPGA and DDR3 SDRAM, to overcome the slow data transmission rate and the operation Complicated, long development cycle, poor configurability and other defects

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