A front-end codec system and method for broadband power carrier communication
A power carrier communication, encoding and decoding technology, applied in distribution line transmission systems, transmission systems, digital transmission systems, etc., can solve the problems of increased chip power consumption, increased chip cost, multiple resources, etc., to reduce chip power consumption, The effect of reducing chip cost and saving hardware resources
Active Publication Date: 2022-02-01
苏州门海微电子科技有限公司
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Problems solved by technology
However, FEC generally involves more complex calculations and consumes more resources
This leads to an increase in chip cost and chip power consumption, resulting in poor economy
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[0062] Embodiment: The following will clearly illustrate this case with drawings and detailed descriptions. After any person skilled in the art understands the embodiment of this case, he can change and modify it by the technology taught in this case without departing from the spirit of this case. with range.
[0063] The terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the present case. Singular forms such as "a", "the", "the", "this" and "the", as used herein, also include plural forms.
[0064] The terms “first” and “second” used herein do not refer to a sequence or order, nor are they used to limit the present application, but are only used to distinguish components or operations described with the same technical terms.
[0065] As used herein, "comprising", "comprising", "having" and the like are all open terms, meaning including but not limited to.
[0066] Regarding the terms used in this artic...
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A front-end encoding and decoding system and method for broadband power carrier communication, the system includes an encoding unit and a decoding unit; the encoding unit includes a first information code memory, a TURBO encoder, a first check code memory and a first address converter The decoding unit comprises the second information code memory, TURBO decoder, the second check code memory and the second address converter; the second information code memory is used to write the LLR after the information code data demapping, the second check code memory It is used to write the PLLR after the check code data is demapped. The structure of the two adopts the same structure as the first information code memory and the first check code memory, and the number of addresses is 8 times that of the latter; the TURBO decoder uses It is used to parse the LLR and PLLR to obtain the information code bit sent by the transmitting end; the second address converter is used to convert the address after channel interleaving into the address before channel interleaving. The present invention saves hardware resources, improves computing efficiency, thereby helps to reduce chip cost and chip power consumption, and has better economy.
Description
technical field [0001] The invention relates to broadband power carrier communication, in particular to a front-end codec system and method for broadband power carrier communication. Background technique [0002] Broadband power line carrier communication technology is the key technology and core support of smart grid. Among them, the introduction of forward error correction code (FEC) has improved the anti-interference ability and stability of power line carrier communication. However, FEC generally involves more complex calculations and consumes more resources. This further leads to an increase in chip cost and chip power consumption, resulting in poor economy. [0003] Therefore, how to solve the above-mentioned deficiencies in the prior art becomes the subject to be studied and solved by the present invention. Contents of the invention [0004] The purpose of the present invention is to provide a front-end codec system and method for broadband power carrier communic...
Claims
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IPC IPC(8): H04L1/00H04B3/54
CPCH04L1/0066H04L1/0071H04B3/54
Inventor 林雄鑫朱忠益
Owner 苏州门海微电子科技有限公司