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A test and analysis method to determine the failure position of gan cascode devices

A test method and device technology, which is applied in the direction of single semiconductor device test, semiconductor/solid-state device test/measurement, semiconductor working life test, etc., can solve the problems of unpacking test failure, tediousness, and insufficient accuracy

Active Publication Date: 2021-09-14
DALIAN UNIV OF TECH +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The unpacking test can confirm the integrity of each position inside the device one by one after unpacking, but because the unpacking process may cause damage to the internal device structure, the failure of the unpacking test is not entirely caused by the aging process
The more precise location of device failure after unpacking can be observed under a high-power optical microscope, but due to the destructiveness and uncertainty of the unpacking process itself, the accuracy of the observation results after unpacking cannot be fully guaranteed
And usually, if you want to determine the location where the device fails after aging, you need to complete all the above-mentioned steps, which is cumbersome, costs and time is spent in batch testing, and it is difficult to analyze, and the accuracy is relatively not high enough

Method used

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  • A test and analysis method to determine the failure position of gan cascode devices
  • A test and analysis method to determine the failure position of gan cascode devices
  • A test and analysis method to determine the failure position of gan cascode devices

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Experimental program
Comparison scheme
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Embodiment 1

[0029] In order to simplify the test process, omit unnecessary test steps, and determine the specific location of device failure through test results, the present invention proposes a test result analysis comparison table, and the specific test steps and analysis methods are as follows.

[0030] figure 1 The internal equivalent circuit diagram of a common normally-off GaN cascode structure is given, and the components in the circuit are labeled for the convenience of description. The numbers 1-8 represent Si MOSFET gate-source channel, Si MOSFET gate-drain channel, GaNHEMT gate-source channel, GaN HEMT gate-drain channel, GaN HEMT gate, Si MOSFET gate, Si MOSFET body active region, GaNHEMT Bulk unintentionally doped layer.

[0031] The test method proposed by the invention is carried out in the state of device packaging. It is divided into three steps:

[0032] The first step is to measure the gate leakage level Igss of the device;

[0033] The second step is to measure th...

Embodiment 2

[0051] The technical points to be protected in the application of the present invention are: (1) Reliability test scheme of cascode structure device in sealing state (2) Comparison table of cascode test result analysis method in sealing state (3) Judgment criteria of cascode structure failure position and failure cause .

[0052] Specific embodiments of the present invention are as follows:

[0053] Step ①: There are two methods for measuring the gate leakage level Igss of the device. The first method is to short-circuit both ends of the drain and source, and apply a voltage to the gate to measure the leakage. The second method is to short the two ends of the gate and source, and to apply a voltage to the drain to measure the leakage. The final conclusions of the two methods are equivalent.

[0054] Step ②: Measure the leakage level of the device under the low drain voltage, ground the source, apply 0 bias to the gate, and apply a small voltage to the drain at the same time,...

Embodiment 3

[0062] The specific embodiment of the method for testing and analyzing the failure position of the GaN cascode device proposed by the present invention is described as follows:

[0063] Step ①: measure the gate leakage level Igss of the device. For devices that fail after aging, short-circuit the two ends of the gate-source or drain-source of the device and ground them, and apply 1-V to the other end th (Si MOS threshold voltage), a small voltage to measure the current level in the loop.

[0064] Step ②: Measure the leakage level of the device at low drain voltage. Ground the source, apply 0 bias to the gate, and apply a small voltage less than 20V to the drain at the same time, and measure the leakage current of the drain at this time.

[0065] Step ③: Measure the leakage level of the device under high drain voltage. Ground the source, apply 0 bias to the gate, and apply a large voltage of 480-750V to the drain at the same time, and measure the leakage current of the drain...

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Abstract

The application discloses a test analysis method for determining the failure position of a GaN cascode device, which belongs to the field of reliability test of semiconductor chips. The technical points are: measure the gate leakage level Igss of the device; measure the drain leakage level Idss@LV of the device under the low drain voltage of the off state; measure the leakage level Idss of the device under the high drain voltage of the off state @HV conducts measurement; the failure location inside the device can be determined through the test result analysis comparison table, and the principle and model of device failure can be clarified at the same time. Beneficial effects: the test and analysis method for determining the failure location of GaN cascode devices described in the present invention simplifies the cumbersome process of traditional testing into three steps, and does not require unpacking steps, and can quickly and accurately obtain the device while ensuring the accuracy of test and analysis results. location and principle of failure.

Description

technical field [0001] The invention belongs to the field of reliability testing of semiconductor chips, and in particular relates to a test and analysis method for determining the failure position of GaN cascode devices. The specific failure location of the device. Background technique [0002] In the application field of power electronic devices, the length of device life also reflects the pros and cons of device performance to a certain extent. Semiconductor device manufacturers will conduct aging tests on devices during the product testing stage to evaluate the reliability of devices. Only by testing and analyzing the devices that fail after aging, and determining the location of failure and the cause of failure, can the product be optimized in terms of design and production in a targeted manner. Therefore, it is particularly important to determine the location of failure of the device. [0003] For GaN materials, due to effects such as polarization, two-dimensional ele...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/66G01R31/26
CPCG01R31/2601G01R31/2642H01L22/14H01L22/20
Inventor 黄火林李飞雨王荣华刘晨阳任永硕梁辉南
Owner DALIAN UNIV OF TECH