Semiconductor structure measurement and boundary feature extraction method and device

Abstract

The present application discloses a semiconductor structure measurement and boundary feature extraction method and device. The boundary feature extraction method includes: acquiring a cross-sectional image of a semiconductor structure output by a transmission electron microscope, including a cross-sectional pattern of at least one hole, and the plane where the cross-sectional pattern is located is perpendicular to the axial direction of the hole; a preset pattern; and identifying the boundary of the first preset pattern, wherein the first preset pattern is composed of polysilicon in the hole. The boundary feature extraction method utilizes the special properties of the interaction between polysilicon and electrons, enhances the contrast of the first preset pattern, and achieves the purpose of clearly identifying the boundary of the first preset pattern.

Description

technical field [0001] The present invention relates to semiconductor technology, and more particularly, to a method and device for measuring and extracting boundary features of semiconductor structures. Background technique [0002] With the miniaturization of semiconductor devices, the critical dimensions of semiconductor devices have been reduced to the nanometer level, which means that the critical dimensions will determine the performance of semiconductor devices. Therefore, it is necessary to accurately measure the critical dimensions and grasp the critical dimensions at the nanometer level. The degree of change has become an indispensable link. [0003] In the prior art, the general simple topography of a semiconductor device or a single and large critical dimension of a semiconductor device can be measured by measuring tools, but for complex structures with small critical dimensions (such as 3D NAND) It is said that the measurement tools in the prior art cannot meet...

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Problems solved by technology

[0003] In the prior art, measurement tools can be used to measure the general simple shape of semiconductor devices or the single and large critical dimensions of semiconductor devices, but for complex structures with small critical dimensions (such as 3D NAND) Said, the measurement tool in the prior art can not meet the needs, the main reasons are as follows:

[0004] 1. For example, when using an electron microscope to observe the channel hole in a 3D memory device, since the photo grayscale of the polysilicon channel layer and the tunneling layer filled in the channel hole are almost the same, the interface between the two cannot be distinguished, so Problems that lead to inaccurate measurements

This error in measurement results will seriously affect the process optimization and electrical performance testing of the product

[0005] 2. When using the existing technology to measure, it is necessary to observe the photos with the naked eye. For structures with complex and small critical dimensions, it is difficult to distinguish the difference manually, and there is a problem of low precision

[0006] 3. Due to the need for manual observation, continuous multiple automatic measurements cannot be realized, and there is a problem of low measurement efficiency, which affects the progress of research and development

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