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High-speed low-power-consumption SAR ADC capacitor mismatch self-calibration method and circuit

A capacitance mismatch and calibration circuit technology, applied in analog/digital conversion calibration/testing, electrical components, electrical signal transmission systems, etc., can solve the problems of low power consumption, capacitance mismatch, etc., and achieve the effect of low cost

Pending Publication Date: 2020-01-14
BEIJING CEC HUADA ELECTRONIC DESIGN CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In these applications, SAR ADC is the most commonly used structure because of its simple structure, small area, and low power consumption. In traditional SAR ADCs, the DAC capacitor array occupies the largest proportion of the area, often accounting for 1% of the entire ADC. / 3 or so, and a large DAC capacitance means a large input capacitance, so in order to further reduce the capacitance size and reduce the input capacitance, it is necessary to design the unit capacitance to be very small, which will bring a large capacitance mismatch, which requires Add capacitance mismatch calibration technology

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  • High-speed low-power-consumption SAR ADC capacitor mismatch self-calibration method and circuit
  • High-speed low-power-consumption SAR ADC capacitor mismatch self-calibration method and circuit
  • High-speed low-power-consumption SAR ADC capacitor mismatch self-calibration method and circuit

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Embodiment Construction

[0015] The present invention will be further described below in conjunction with accompanying drawings and examples.

[0016] The present invention is a capacitance mismatch self-calibration method and circuit applied in a high-speed SAR ADC, and its circuit framework is as follows figure 1 As shown, the entire ADC circuit is mainly composed of a calibration circuit module 101 , a calibration capacitor module 102 , a SAR ADC core conversion module 103 , and an on-chip linear waveform generator 104 .

[0017] The SAR ADC core conversion module contained in the calibration circuit is a full-capacitance asynchronous clock SAR ADC, and its high n bits (C1, C2,...) need to be calibrated, and the value of n is related to the number of bits of the designed ADC, which needs to be calibrated The capacitance is 205; each capacitor that needs to be calibrated corresponds to the capacitance segment of different segments in the calibration capacitor module, and the calibration capacitor on...

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Abstract

The invention provides a capacitor mismatch calibration technology applied to a high-speed low-power-consumption successive approximation type digital-to-analog converter (SAR ADC). The capacitance mismatch foreground calibration method is a capacitance mismatch foreground calibration scheme based on code density statistics, the calibration circuit cost is low, and high-speed low-power-consumptiondesign is easy to realize. The circuit mainly comprises an SAR ADC core conversion module, a calibration circuit module, a calibration capacitor module and an on-chip linear waveform generator. Afterthe system is powered on, the ADC firstly enters a calibration mode, capacitors needing to be calibrated are sequentially calibrated from a low position to a high position, and at the moment, the SARADC core conversion module samples and converts signals generated by the on-chip linear waveform circuit and outputs calibration codes of all the capacitors needing to be calibrated; after calibration is finished, the ADC enters a normal conversion mode, and the SAR ADC core conversion module samples and converts external input; and the digital calibration logic controls the capacitor bottom plate of the calibration capacitor module to be connected with a corresponding potential according to the calibration code and ADC digital output, and completes comparison each time successively.

Description

Technical field: [0001] The invention relates to a self-calibration method and circuit for capacitance mismatch in a SAR ADC, and is mainly used in the design of ADC chips or SOCs in high-speed, low-power and small-size applications. Background technique: [0002] Since the invention of the integrated circuit, it has developed rapidly along Moore's Law, the process line width has been continuously reduced, and the integration degree has been continuously increased. The continuous improvement of technology is crucial to the development of digital circuits. In today's society, the processing capability of digital signals and the development of digital storage technology are quite mature. As a bridge between the analog world and digital circuits, the analog-to-digital converter (AnalogDigital Converter, ADC) is a very important module. It is used in various fields including communications, energy, medical, instrumentation and even the rapidly developing AI field. widely used. ...

Claims

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Application Information

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IPC IPC(8): H03M1/10H03M1/46
CPCH03M1/1009H03M1/468
Inventor 谷宪
Owner BEIJING CEC HUADA ELECTRONIC DESIGN CO LTD
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