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Planarization process method

A planarization process and process technology, applied in the field of planarization process, can solve problems such as reducing the performance of semiconductor devices, and achieve the effect of ensuring height and size

Active Publication Date: 2020-01-24
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, in the actual process, the height of the final metal gate structure is easily lower than the set target height, which reduces the performance of semiconductor devices

Method used

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Examples

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no. 1 example

[0035] Please refer to figure 1 , the metal material layer 120 is formed on the semiconductor substrate 100 , and the metal gate 130 is formed in the semiconductor substrate 100 and the metal material layer 120 .

[0036] The semiconductor substrate 100 serves as a process basis for forming semiconductor devices. The material of the semiconductor substrate 100 is at least one of the following materials: polysilicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI) and silicon-on-insulator Silicon germanium (SiGeOI), etc. In the embodiment of the present invention, the material of the semiconductor substrate 100 is polysilicon, and the semiconductor substrate 100 also contains other structures, such as: metal plugs, metal connection layers, dielectric layers and other structures, or contains these structural components Other semiconductor devices are not specifically limited here.

[0037] In the embodiment of the present in...

no. 2 example

[0072] The difference between the second embodiment and the first embodiment is that the first grinding process is used to directly grind the second part of the metal material layer, the sidewall and part of the metal gate, so that the second part of the remaining metal gate has the first grinding process. a height. Subsequent process steps are consistent with the first embodiment.

[0073] Please refer to Image 6 , providing a semiconductor substrate 200 , sidewalls 210 , a metal material layer 220 and a metal gate 230 .

[0074] The structures, functions, and positional relationships of the semiconductor substrate 200 , sidewalls 210 , metal material layer 220 , and metal gate 230 are consistent with those of the first embodiment, and will not be repeated here.

[0075] Please refer to Figure 7 , using a first grinding process to grind the metal material layer 220 , the second part of the partial metal gate 230 and the sidewall 210 .

[0076] The purpose of performing ...

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PUM

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Abstract

The invention discloses a planarization process method. The method comprises the following steps that: a semiconductor substrate and a metal material layer are provided, wherein the metal material layer is arranged on the semiconductor substrate, metal gates and side walls are formed in the semiconductor substrate and the metal material layer, the side walls are formed on two side walls of each metal gate, the first parts of the metal gates are formed in the semiconductor substrate, and the second parts of the metal gates are formed in the metal material layer; a first grinding process is adopted to grind the metal material layer or grind parts of the side walls and the second parts of the metal gates, so that the second parts of the remaining metal gates have a first height; and a secondgrinding process is performed on the remaining metal gates and side walls to expose the semiconductor substrate, the first grinding process and the second grinding process respectively have grinding rate ratios to the metal material layer or the metal gates and the side walls. The two-step process is adopted to grind the second parts of the metal gates, so that the height of the final metal gate structures can be well controlled.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a planarization process method. Background technique [0002] In the manufacturing process of semiconductor devices, after filling the grooves with metal materials, grinding is required to remove excess metal materials and planarize the surface of the metal material layer to facilitate subsequent deposition of other materials. For example, in the process of forming the metal gate, generally the top of the metal material is higher than the top of the metal gate, and the height of the metal gate is controlled by a chemical mechanical planarization process. [0003] However, in an actual process, the height of the final metal gate structure is likely to be lower than the set target height, which reduces the performance of the semiconductor device. [0004] Therefore, there is an urgent need for a planarization process method that controls the height of the metal gate duri...

Claims

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Application Information

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IPC IPC(8): H01L21/306H01L21/321
CPCH01L21/30625H01L21/3212
Inventor 纪登峰金懿张庆刘璐蒋莉
Owner SEMICON MFG INT (SHANGHAI) CORP