Vertical cavity surface emitting laser chip screening method and device

Abstract

The invention discloses a method for screening a vertical cavity surface emitting laser chip. The method comprises the step of performing aging screening on the VCSEL chip; before the aging screening, the VCSEL chip is pre-screened, and the specific method is as follows: the VCSEL chip is subjected to DC current pulse Perform a cyclic impact, and remove the failed chip through a performance test after the impact is completed; the current size of the DC current pulse is Ith+S, the pulse width is 50ms to 200ms, and Ith is the threshold current of the vertical cavity surface emitting laser chip , the value range of S is 20 mA ~ 40 mA. The invention also discloses a vertical cavity surface emitting laser chip screening device. The invention can effectively remove bad chips with black line defects and oxide layer crack defects in the chip quantum well region which are difficult to completely remove in the prior art, thereby greatly reducing the leakage rate of aging screening and improving the efficiency of aging screening.

Description

technical field [0001] The invention relates to a chip screening method, in particular to a vertical cavity surface emitting laser (Vertical Cavity Surface Emitting Laser, VCSEL for short) chip screening method. Background technique [0002] Vertical cavity surface emitting lasers are very promising optoelectronic devices in the optical communication industry. Compared with traditional edge-emitting laser chips, this type of laser chip has a small far-field divergence angle, a narrow and round emitted beam, high coupling efficiency, low threshold current, no need for cleavage, and performance testing can be performed directly at the wafer level. The manufacturing cost is greatly reduced; the advantage of being easy to manufacture array devices in two-dimensional integration. [0003] There are three main ways to realize the lateral confinement of carriers near the VCSEL active region, simple chemical wet method, ion implantation method and wet oxidation method. The most com...

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Problems solved by technology

[0004] The aging screening method of VCSEL chips is usually to apply high temperature and current stress to the chip for a certain period of time (usually the aging temperature is 85 ℃ ~ 150 ℃, and the current range is 8mA ~ 14mA) to accelerate the life of the chip. By testing the performance parameters of the chip Changes to remove early-failure chips in a short period of time, but the existing aging screening conditions cannot 100% remove early-failure chips, especially the dark line defects (Dark Line Defects) and oxidation in the quantum well area of ​​the chip Layer crack defects, the existing aging screening methods cannot be effectively found and eliminated, so there will be early failure products that miss the screen, and the missed screen products will appear in the subsequent use process, which will lead to an increase in scrap costs and a higher rate of missed screening The higher the corresponding scrap cost

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