Cache access system

A cache and access system technology, applied in image communication, selective content distribution, electrical components, etc., can solve the problems of wasting hardware space, limited cache efficiency, and high frequency of cache misses

Inactive Publication Date: 2020-02-07
MSTAR SEMICON INC
View PDF8 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] Although the cache can reduce the need to read data from the external main memory through the bus, if the data required by the processor each time is not in the cache, that is, the frequency of cache misses is too high, the cache can not The benefits may still be very limited, or even waste valuable hardware space

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Cache access system
  • Cache access system
  • Cache access system

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0038] figure 1 It is a schematic diagram of a cache access system 100 according to an embodiment of the present invention. The cache access system 100 includes a cache 110 and a control unit 120 . In some embodiments of the present invention, the cache access system 100 can be applied to image compression.

[0039] In practice, in order to improve the utilization efficiency of hardware resources, when compressing the data of a frame, a frame can be divided into multiple image tiles (tiles) and / or multiple image blocks (blocks). Each image block in a frame is compressed sequentially. For example, the original picture can be divided into 2 A x2 B image tiles, and each image tile contains 2 ΔX x2 ΔY blocks, wherein A, B, ΔX and ΔY are natural numbers, that is, zero or positive integers.

[0040] figure 2 It is a schematic diagram of the image tiles and image blocks of the original picture IMG1 according to an embodiment of the present invention. figure 2 In an exampl...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

Responding to a request for reading the compressed image data of a first pixel of a first image block, a control unit controls the display unit according to (X + delta X) least significant bits of thehorizontal coordinates of the first pixel in the original picture, (Y + delta Y) least significant bits of the vertical coordinates of the first pixel in the original picture, the address of the first pixel corresponding to the external memory and the address of the starting pixel of the first image block corresponding to the external memory. A target index of the first pixel in the cache is generated, a target label of the first pixel is generated according to the A most significant bits of the first pixel in the horizontal coordinates of the original picture and the B most significant bitsof the first pixel in the vertical coordinates of the original picture, and the corresponding label of the corresponding cache line corresponding to the target index is compared with the target labelof the first pixel in the cache.

Description

technical field [0001] The present invention relates to a cache access system, in particular to a cache access system capable of maintaining the two-dimensional spatial relationship of pixels. Background technique [0002] The cache can include multiple cache lines, and each cache line can store at least one piece of corresponding data. In order for the processor to confirm whether the required data is stored in the cache, each cache line has its corresponding valid bit (valid bit), tag (tag), index (index) and offset value (offset) and other information for the processor to check and confirm. Table 1 illustrates the corresponding relationship between valid bits, tags, indexes and offset values ​​and data addresses M[11:0] of a cache line in the prior art. [0003] Table 1: [0004] Valid bit Label index offset value 0 / 1 M[11:9] M[8:5] M[4:0] [0005] In Table 1, if the address of each piece of data in the main memory is expressed as M[11:0] in ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Applications(China)
IPC IPC(8): H04N21/231H04N21/433
CPCH04N21/23106H04N21/4331
Inventor 林和源
Owner MSTAR SEMICON INC
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products