A kind of nand Flash timing test method

Abstract

The invention discloses a NAND Flash timing test method, the steps comprising: obtaining all stored data in the NAND Flash; performing a read operation on the NAND Flash, and moving the sampling pulse position, collecting the read data, and obtaining a plurality of collected data; The stored data is compared with the collected data, and the comparison result of each byte in the Page is stored in the error capture memory; the error capture memory is divided into multiple areas, and the data valid window time t corresponding to each area is obtained DVW and data valid area time t strobe ;According to the corresponding t of each region DVW and t strobe , to determine whether the NAND Flash is faulty. This timing test method uses a sub-regional method to test the timing parameters to make the measured parameters more accurate. The application of multi-clock setting memory enables ATE to overcome the interference caused by the timing offset of the chip in DDR3 mode and correctly collect the output data of the chip. Functional testing provides a reliable testing environment without improving the hardware of ATE equipment, saving testing costs.

Description

technical field [0001] The invention relates to the technical field of memory chip testing, in particular to a NAND Flash timing testing method. Background technique [0002] At present, due to the high degree of chip integration, testing of NAND Flash chips is usually performed by automatic test equipment (ATE); during the test process, it is judged whether the chip has a fault by comparing whether the data input and output by the chip are the same. [0003] Most of the existing NAND Flash chip interfaces are in DDR3 mode. In DDR3 mode, the data transmission rate is 800MT / S, and the data transmission cycle is 2.5ns. As the data transmission rate increases, the parasitic capacitance interference caused by defects caused by the ATE process The phenomenon will be amplified; specifically, when the operating frequency of the chip is high, the charge stored in the parasitic capacitance will interfere with the circuit characteristics. Because the pulse interval is too short, the ...

AI Technical Summary

Problems solved by technology

[0004] In order to overcome the technical problem that existing automatic test equipment cannot normally carry out timing test to NAND Flash under DDR3 mode, the present invention provides a kind of NAND Flash timing test method

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