Implementation method of adaptive fault-tolerant data parallel computing for multi-core processors
A multi-core processor, parallel computing technology, applied in the field of multi-core processors, can solve the problems of multi-core processor failure, failure, parallel programs cannot be executed correctly, etc.
Active Publication Date: 2022-06-07
NAT UNIV OF DEFENSE TECH
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[0004] However, some cores of multi-core processors may fail. For example, satellites operating in space are affected by space particle radiation. Multi-core processors will also have yield problems during production. Some multi-core processors will have partial core failure problems. Now In existing technologies, when multi-core processors are used to perform data parallel computing, the data parallel program divides data tasks according to the original number of processing cores, so a problem is usually faced: when some cores of the multi-core processor fail, the parallel program cannot Correct execution, in order to ensure correct execution, certain modifications must be made
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[0034] The present invention will be further described below with reference to the accompanying drawings and specific preferred embodiments, but the protection scope of the present invention is not limited thereby.
[0035] The multi-core processor used in this embodiment is as follows: figure 1 As shown, including homogeneous cores numbered 0, 1, 2,..., q-1 in sequence, each core shares off-chip memory, calculation data and calculation results are stored in the shared off-chip memory, and each core passes the data Parallel computing completes computing tasks together. In a specific application embodiment, the data-parallel calculation of performing block matrix multiplication (C=C+A*B) for a multi-core processor is as follows: figure 2 As shown in the figure, the parallel computing method of data parallel is adopted, and the C and B matrices are divided into blocks according to the column and the basic block size BLOCK is used as the unit. The single calculation task under ...
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The invention discloses a multi-core processor-oriented adaptive fault-tolerant data parallel computing implementation method. The steps of the method include: step 1: setting a global register R; step 2: when the target multi-core processor is required to perform data parallel computing, the target multi-core After each core of the processor starts, read the global register R separately; Step 3: each core of the target multi-core processor calculates the address of the data block required by each core and the remaining calculation of the current calculation task Data volume, and calculate the actual load of each core for each calculation; Step 4: Each core of the target multi-core processor performs calculations according to the data block address and actual load for each calculation; Step 5: Complete all calculation data volume Exit after the calculation. The invention can self-adaptively and correctly execute data parallel calculation when some cores fail, and has the advantages of simple realization method, good self-adaptive fault-tolerant performance, flexible application and the like.
Description
technical field [0001] The invention relates to the technical field of multi-core processors, in particular to an adaptive fault-tolerant data parallel computing implementation method for multi-core processors. Background technique [0002] With the increasingly prominent problems of power consumption and heat dissipation, energy consumption has gradually become an increasingly important factor affecting high-performance computing systems, making the processor architecture develop towards multi-core. At present, multi-core processors have occupied high-performance computing. The vast majority of the market, in the embedded application platform, the application of multi-core processors is also more and more extensive. [0003] There are two main types of parallel methods for multi-core processors: data parallel and task parallel, in which data parallel applications such as multi-channel network traffic processing, multiple audio / video channel data processing, etc., task paral...
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IPC IPC(8): G06F9/50
CPCG06F9/5044G06F9/505Y02D10/00
Inventor 刘仲郭阳扈啸田希邓林陈海燕李勇吴虎成孙书为李程
Owner NAT UNIV OF DEFENSE TECH