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Delay locked loop (DLL) employing pulse to digital converter (PDC) for calibration

A delay-locked loop and digital converter technology, applied in the field of delay-locked loops, can solve problems such as limiting practical applications

Active Publication Date: 2020-02-21
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, some pulse-to-digital converters (PDCs) can have a limited linear range and thus limit their practical application

Method used

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  • Delay locked loop (DLL) employing pulse to digital converter (PDC) for calibration
  • Delay locked loop (DLL) employing pulse to digital converter (PDC) for calibration
  • Delay locked loop (DLL) employing pulse to digital converter (PDC) for calibration

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Embodiment Construction

[0023] The detailed description set forth below in connection with the accompanying figures is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details to provide a thorough understanding of various concepts. It will be apparent, however, to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0024]A pulse-to-digital converter (PDC) may use analog components such as RC filters, comparators, etc. to extract pulse width measurements as input to a delay-locked loop (DLL) for calibration. However, the use of analog components may not scale well to smaller feature sizes and may limit their speed of operation. DLLs that use PDCs with analog components su...

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PUM

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Abstract

Aspects of the disclosure are directed to generating a quadrature clock signal from an in-phase clock signal. In accordance with one aspect, a delay locked loop (DLL), including a first pulse to digital converter (PDC) to generate a first pulse width measurement, wherein the first pulse width measurement includes a first sign and a first magnitude; a second pulse to digital converter (PDC) to generate a second pulse width measurement, wherein the second pulse width measurement includes a second sign and a second magnitude; a digital loop filter coupled to the first PDC and the second PDC, thedigital loop filter to generate a filtered comparison output based on the first pulse width measurement and the second pulse width measurement; and a first delay generation block to generate a quadrature clock signal based on the filtered comparison output and an in-phase clock signal.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to and benefit of U.S. Nonprovisional Patent Application No. 15 / 644,426 filed in the U.S. Patent and Trademark Office on July 7, 2017, which is hereby incorporated by reference in its entirety , and as fully set forth below and for all applicable purposes. technical field [0003] The present disclosure relates generally to the field of delay locked loops, and more particularly to delay locked loops for generating quadrature clock signals from in-phase clock signals. Background technique [0004] Several forms of converters can be used in electronic circuits to convert one signal in one domain to another signal in another domain. For example, a pulse-to-digital converter (PDC) is an electronic circuit that converts the width of a pulse (measured in units of time) into a digital representation. Different implementations of pulse-to-digital converters can be used in different applicati...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/081H03L7/085
CPCH03L7/0814H03L7/085H03L7/0816G04F10/005
Inventor E·黑路B·班迪达
Owner QUALCOMM INC
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