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Image encoding and decoding and network transmission method and device based on FPGA

A technology of network transmission and image encoding, applied in the system design of video image encoding and decoding, and data network transmission, it can solve the problem of not supporting 1000M Ethernet, and achieve a large follow-up development space, efficient and real-time Ethernet data transmission, The effect of performance and functionality improvements

Active Publication Date: 2020-02-28
NO 709 RES INST OF CHINA SHIPBUILDING IND CORP
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Problems solved by technology

They can support 10M / 100M Ethernet data communication, but not 1000M Ethernet

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  • Image encoding and decoding and network transmission method and device based on FPGA
  • Image encoding and decoding and network transmission method and device based on FPGA
  • Image encoding and decoding and network transmission method and device based on FPGA

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Embodiment Construction

[0069] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention.

[0070] see figure 1 , the FPGA-based image encoding and decoding and network transmission method and device system network diagram provided in the embodiment of the present invention includes five parts: the host computer at the encoding end, the encoding end, the network switching device, the decoding end, and the upper computer at the decoding end. The terminal and the decoding terminal are the core components of the system. Both the encoding end and the decoding end are connected to the network switching device through the network port. The system can process the video images collected from the camera in real time, and use a dedicated JPEG2000 encoding ASIC chip to encode the captured images in real time according to the JPEG2000 standard, and the encoded data is transmitt...

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Abstract

The invention discloses an image encoding and decoding and network transmission method and device based on an FPGA. And the FPGA is used for configuring and controlling the JPEG2000 encoding and decoding chip, the network communication chip and the like under configuration instructions of the encoding end upper computer and the decoding end upper computer respectively. And the encoding end receives the video image and converts the video image into a digital format, and the JPEG2000 encoding chip encodes the acquired video image. Coded data output by the coding chip is buffered and then sent tothe network communication chip so as to generate a network data message and send the network data message to the Ethernet. And the decoding end receives video image data on the Ethernet by reading anetwork data message of the network communication chip. And the decoding end buffers the network message data, sends the buffered network message data to a JPEG2000 decoding chip for image decoding, and then restores and displays a video image. According to the invention, the function of each part is brought into full play, and the requirements of real-time performance of video image coding and decoding and network transmission are met.

Description

technical field [0001] The invention relates to the technical field of system design of video image encoding and decoding, and the field of network transmission of data. Background technique [0002] As the successor of JPEG, JPEG2000 is different from the traditional JPEG standard based on discrete cosine transform. JPEG2000 is based on discrete wavelet transform and adopts the embedded coding technology EBCOT with optimal truncation function to obtain advanced compression performance. [0003] In the hardware solutions to realize JPEG2000 image decoding, generally speaking, there are mainly several methods such as FPGA-based hardware algorithm implementation, DSP processor-based system implementation, and application-specific integrated circuit implementation. Although the hardware implementation based on the FPGA platform can speed up the processing speed, the digital circuit design and implementation of the algorithm is also very difficult, and the design is relatively c...

Claims

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Application Information

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IPC IPC(8): H04N19/42
CPCH04N19/42
Inventor 亢琰
Owner NO 709 RES INST OF CHINA SHIPBUILDING IND CORP
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