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Fast access dram with 2 cell-per-bit, common word line, architecture

A storage unit, common word technology, applied in information storage, static memory, digital memory information and other directions, can solve the problems of weak reading signal, slow reading, etc.

Inactive Publication Date: 2020-04-07
OMNIVISION TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0002] Dynamic random access memory (RAM) (DRAM) typically occupies much less area per bit than static RAM (SRAM), however single-transistor (1-T) memory cell DRAM usually provides a sufficiently weak read signal, i.e. 1-T DRAM reads much slower than SRAM

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  • Fast access dram with 2 cell-per-bit, common word line, architecture
  • Fast access dram with 2 cell-per-bit, common word line, architecture
  • Fast access dram with 2 cell-per-bit, common word line, architecture

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Embodiment Construction

[0011] figure 1 A read channel 100 of a 1-T DRAM is shown in . also refer to figure 2 , the precharge line Pch provides a neutral value between a logic 1 value and a logic 0 value from the reference voltage Vdd1 during the precharge interval 202 to precharge the bit lines B0-B5 and then zero the Pch line. In conventional 1-T DRAM, a selected single select line 204 (e.g., Sel1) is pulled up by row decoder 130 so that charge from capacitor 104 can pass through select transistor 106 in selected memory cell 108 to bitlines B0-B2 of the selected half 120 of the array, while the remaining bitlines B3-B5 driven by the second row decoder 132 remain static and no charge passes through the select transistors in the unselected memory cells 134 . Charge from capacitor 104 is shared onto the bitlines B0-B2 of the selected half of the array, causing a voltage change 210, and then during compare enable signal 206, differential sense amplifier 110 compares these bitlines to the unselected...

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Abstract

In a system, a 1T DRAM a decoder drives word lines, each driving enable transistors of true and complement DRAM cells; true DRAM cells being coupled to true bit lines, with complement DRAM cells coupled to complement bit lines. Differential sense amplifiers each receive true and complement bit lines. In a method of writing and reading DRAM, a DRAM is provided with common word lines feeding true and complement cells attached to true and complement bit lines. Writing the DRAM includes applying data to true bit lines with complement data on complement bit lines; then pulsing a selected word lineto write data into true and complement cells. Reading requires pulsing precharge lines to reset true and complement bit lines; selecting a single word line to read the true and complement cells onto true and complement bit lines; and sensing differences between true and complement bit lines.

Description

technical field [0001] The present application relates to dynamic random access memory (DRAM) and methods of writing and reading dynamic random access memory. Background technique [0002] Dynamic random access memory (RAM) (DRAM) typically occupies much less area per bit than static RAM (SRAM), however single-transistor (1-T) memory cell DRAM usually provides a sufficiently weak read signal, i.e. 1-T DRAM reads much slower than SRAM. Contents of the invention [0003] In an embodiment, a dynamic random access memory (DRAM) with one-transistor memory cells has a decoder-driver configured to drive word lines, each word line driving a true one-transistor DRAM memory cell (true one-transistor DRAM) cell) and the enable transistor of the complement one-transistor DRAM cell; the original code DRAM memory cell is connected to the original code bit line, and the complement one-transistor DRAM is connected to the complement code bit line. The differential sense amplifiers each r...

Claims

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Application Information

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IPC IPC(8): G11C11/4063G11C7/10
CPCG11C7/1045G11C11/4063G11C11/404G11C11/4091G11C11/4094G11C11/4097G11C11/4085G11C11/4087
Inventor 丁台衡陈家明尹贤洙
Owner OMNIVISION TECH INC
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