SpaceFibre node IP core based on FPGA

A node and routing technology, applied in the field of aerospace engineering, can solve problems such as no productization

Active Publication Date: 2020-04-17
NAT SPACE SCI CENT CAS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] At present, the SpaceFibre protocol is still in the research stage and has not been commercialized

Method used

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  • SpaceFibre node IP core based on FPGA
  • SpaceFibre node IP core based on FPGA
  • SpaceFibre node IP core based on FPGA

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Embodiment Construction

[0099] The technical solution of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0100] The present invention designs an easy-to-transplant SpaceFibre Codec IP core node. The IP implements the functions of four virtual channel caches and a single channel. The bottom layer can use the GTX IP core resources in the FPGA, which is convenient for transplantation and implementation on the FPGA. The IP core provides a management interface through which parameter configuration and state machine reading can be performed. The IP core can be used as an interface for spaceborne equipment, sending spaceborne data to SpaceFibre's routing network for routing, and realizing the interconnection of large-scale spaceborne equipment through the routing network.

[0101] Such as figure 1 As shown, the SpaceFibre protocol is divided into five layers: management layer, network layer, data link layer, multi-channel layer, channel layer, and ph...

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Abstract

The invention discloses a SpaceFibre node IP core based on an FPGA. The IP core comprises a management layer, a data link layer, a channel layer and a physical layer. The management layer is used forconfiguring an upper-layer command to the command register in each layer and enabling the upper layer to read the state of the state register in each layer. The data link layer is used for realizing QoS-based sending scheduling, flow control and FDIR mechanism-based error recovery of various data when a node is located at a sender, and realizing receiving and confirmation of various data when thenode is located at a receiver. The channel layer is used for realizing connection control with channels of other nodes, encoding the data sent by the data link layer and decoding the data sent to thedata link layer. The physical layer is used for completing sending and receiving of serial data streams by using a physical medium, realizing serial-parallel conversion of sending and receiving through parameter configuration and providing clock recovery during receiving.

Description

technical field [0001] The invention relates to the field of aerospace engineering, in particular to an IP core used for data transmission and network interconnection between various loads in space missions, and in particular to an FPGA-based SpaceFibre node IP core. Background technique [0002] With the continuous development of aerospace technology and the increase in the complexity of aerospace tasks, aerospace data is developing in the direction of large-scale, diverse, and high-speed. Traditional interconnection buses such as 1553B bus, CAN bus, and RS485 bus are increasingly difficult to meet the needs of current and future aerospace data processing. SpaceWire is a bus protocol promulgated by ESA (European Space Agency). Compared with traditional buses, the speed has been significantly improved, up to 400Mbps. However, due to the increase in the amount of data in engineering applications and SpaceWire's own mechanism problems, such as no confirmation mechanism for th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04B7/185
CPCH04B7/18515H04B7/18519
Inventor 祝平安军社朱岩江源源柳萌高润莲郑静雅赵允齐
Owner NAT SPACE SCI CENT CAS
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