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Efficient memory access address bit flipping statistical device

A technology for accessing memory addresses and memory, which is applied in the field of high-efficiency memory address bit flip statistics devices, which can solve problems such as incompleteness and inaccuracy, and achieve the effects of convenient operation, simple device structure, and simple implementation

Inactive Publication Date: 2020-04-28
NAT UNIV OF DEFENSE TECH
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  • Summary
  • Abstract
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  • Claims
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Problems solved by technology

[0003] The technical problem to be solved by the present invention: Aiming at the above-mentioned problems of the prior art, an efficient statistical device for memory access address bit inversion is provided. Accurate and incomplete problems have the advantages of simple implementation, convenient operation, accurate and comprehensive statistics of address bit flip information when applications access memory, so as to effectively guide the optimization of memory address mapping

Method used

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  • Efficient memory access address bit flipping statistical device
  • Efficient memory access address bit flipping statistical device
  • Efficient memory access address bit flipping statistical device

Examples

Experimental program
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Embodiment Construction

[0024] Such as figure 1 As shown, the memory access address bit flip statistics device of this embodiment includes:

[0025] The bit flip monitoring array is mounted on the storage bus of the high-bandwidth memory, and is used to trigger the access count of the corresponding storage channel according to each effective access of the storage channel;

[0026] A bitwise accumulator array, used to record the access count of each storage channel;

[0027] The control part is used for enabling and resetting the storage channel access statistics module and providing an external access count reading operation.

[0028] from figure 1 It can be seen from the figure that the memory access address bit inversion statistics device in this embodiment is composed of a bitwise accumulator array, a bit inversion monitoring array and a control unit. The bit flip monitoring array is directly connected to the memory access address bus, and is used to monitor whether each bit address flips, and ...

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Abstract

The invention discloses an efficient memory access address bit flipping statistical device, which comprises a bit flipping monitoring array used for triggering page view counting of a corresponding storage channel according to each effective access of the storage channel; a bitwise accumulator array which is used for recording the page view count of each storage channel; a control part which is used for enabling and resetting and providing a read operation; a storage controller which comprises a storage body and the statistical device. According to the method, the actual memory access addressbit flipping rate is directly counted, the problem that a traditional method is inaccurate and incomplete is avoided, and the method has the advantages of being easy to implement, convenient to operate and capable of accurately and comprehensively counting the address bit flipping information when the application accesses the memory, and therefore optimization of memory address mapping can be effectively guided.

Description

technical field [0001] The invention relates to the field of processors, in particular to an efficient memory access address bit flip statistics device. Background technique [0002] As processors continue to evolve, memory efficiency is becoming more and more limiting to the overall performance of the processor. The address mapping method is one of the key factors affecting storage efficiency. An efficient address mapping method can effectively reduce storage latency, thereby greatly improving storage efficiency. Therefore, how to optimize the address mapping method plays a very important role in the overall performance of the processor. The flip rate of address bits is important information to guide address mapping optimization. The current typical address mapping optimization method is to obtain address change information through offline simulation of the program, and perform corresponding mapping optimization based on this information. However, affected by factors such...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/06
CPCG06F12/0646
Inventor 王耀华刘胜唐冬灯郭阳鲁建壮陈小文陈海燕刘仲雷元武刘畅张洋张显金志成
Owner NAT UNIV OF DEFENSE TECH
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