Low-power transistor device with radiation-hardened structure and preparation method thereof

Abstract

A low-power transistor device with a radiation-resistant hardened structure, characterized in that it includes a substrate, a buried oxide layer on the substrate, a bulk silicon layer on the buried oxide layer, and a bulk silicon layer on the The source region and the drain region in the middle and both sides of the layer, the gate oxide layer on the bulk silicon layer, the gate stack structure on the gate oxide layer, and the gate stack structure is from bottom to top The order is lower plate metal layer / ferroelectric layer / upper plate metal layer, or from bottom to top is ferroelectric layer / upper plate metal layer. The transistor device of the present invention realizes that the channel potential is greater than the external gate voltage by fabricating a gate stack structure on the gate oxide layer, breaks through the sub-threshold swing of 60mV / dec under the thermodynamic limit, reduces the operating voltage and thus reduces the power consumption of the device At the same time, through multiple step-by-step ion implantation, the source-drain junction depth with the same thickness as the bulk silicon layer is obtained, so that the source-drain junction is in contact with the buried oxide layer at the bottom, and the anti-single particle radiation ability of the device is improved.

Description

technical field [0001] The invention relates to electronic device technology, and belongs to the technical fields of space environmental effects, nuclear science and low-power circuit application, and more specifically, relates to a low-power transistor device with a radiation-resistant hardened structure and a preparation method thereof. Background technique [0002] Space charged radiation particles mainly include heavy ions, electrons, protons and X-rays. These charged particles interact with transistor devices to produce ionizing radiation effects, single event effects, and displacement radiation effects. The traditional anti-radiation strengthening methods for devices usually use anti-radiation coatings or SOI technology. Among them, SOI is divided into fully depleted SOI and partially depleted SOI (PDSOI). For partially depleted SOI, It has a floating body effect, which leads to a parasitic diode amplification effect and increases the ability of sensitive storage node...

AI Technical Summary

Problems solved by technology

For fully depleted SOI, it can reduce the ability of sensitive storage nodes to collect radiated charges, but it has high requirements for the thickness of the top silicon layer, which is difficult and costly to realize in the process

[0003] At the same time, with the improvement of integrated circuit integration, power consumption and radiation resistance have become the main problems limiting its development, so it is urgent to develop radiation-resistant transistor devices with low power consumption

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